IP Methodology and Automation Engineer

The Role And Impact

As a Physical Design Methodology Engineer, you will drive innovation in the development and enhancement of tools, flows, and methods (TFM) that are essential for Intel's physical design implementation across IPs and SoCs. Your work will directly impact the efficiency, quality, and scalability of chip designs, enabling Intel to deliver robust, high-performance, and power-optimized solutions to market. Collaborating with multidisciplinary teams, you will identify gaps, propose transformative changes, and shape the future of physical design methodology, ensuring Intel stays ahead in the ever‑evolving semiconductor industry.

• Conceptualize, document, and design TFMs used in physical design implementation for IPs and SoCs.
• Establish regression flows and drive improvements in RTL to GDS flows.
• Develop and implement methodologies to optimize power, performance, area, and timing in physical design constraints.
• Create innovative scripts, checkers, and CAD-based automation to simplify and accelerate design processes.
• Analyze retrospective data on current designs to identify quality and efficiency gaps, driving incremental and transformative improvements.
• Partner with cross‑functional teams, including physical design, circuit design, CAD, RTL, tool/flow owners, and third‑party vendors, to improve methodologies and ensure alignment.
• Lead initiatives to develop advanced physical design techniques for floor planning, clock tree synthesis, place and route, and multi‑power plane (MPP/UPF) designs.
• Support the integration of new tools and methods into existing design workflows, ensuring seamless adoption and scalability.

• Architect, Design, develop, and maintain robust regression and QA automation frameworks specifically for Memory & Mixed signal Hard IP, ensuring comprehensive validation and signoff automation systems with scalability and performance optimization.
• Integrate automation frameworks with existing development pipelines, develop full‑stack solutions for data management and reporting, and create APIs/interfaces for seamless tool integration across various systems.
• Implement monitoring and alerting mechanisms for automated test execution, continuously improve testing processes, version control, automation coverage, and ensure framework reliability and performance standards.
• Build comprehensive validation systems that integrate with multiple tools and platforms, focusing on scalability, maintainability, and continuous improvement of QA methodologies for semiconductor IP verification.

• Bachelors with 8+ years of experience or Master's degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of professional experience; or PhD with 2+ years of experience.
• Expertise with EDA tools, physical design flows, and methodologies.
• Experience in TCL and PERL scripting for automation and flow development.
• Experience with SoC integration and RTL to GDS design flows.

• Hands‑on experience with design optimization techniques, including synthesis, clock tree synthesis, place and route, and floor planning.
• Experience with the following:
  • Multi‑power plane designs and integration of UPF methodologies.
  • Analyze and improve physical design performance metrics (power, timing, area).
• Leadership & Communication:
  Demonstrated project management experience handling multiple concurrent projects with excellent cross‑team collaboration skills and proven ability to lead technical execution and drive results.
• Programming & Development
  
  Skills:
  
  Expert‑level proficiency in Python, Perl, Tcl, and SKILL with full‑stack development experience and proven ability to build and maintain large‑scale automation frameworks for complex technical environments.
• CI/CD & Database
  
  Experience:
  
  Hands‑on experience with Jenkins, Git Lab CI platforms, SQL/No
  
  SQL databases, and integrating AI/ML technologies into automation frameworks for enhanced testing capabilities.
• Semiconductor Domain Expertise:
  Deep understanding of semiconductor IP design flow, verification processes, and EDA tools combined with strong analytical and…