Sr. Physical Design Engineer, Annapurna Labs

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago—even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

• Work with RTL/logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs for physical design closure
• Drive IO/Core subsystem/block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
• Develop physical design methodologies
• Evaluate 3rd party IP and provide recommendations
• Be a highly-valued member of our start‑up like team through excellent collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams

• Experience scripting with Python, Perl, Bash or Power Shell
• BS + 8 years or MS + 6 years in EE/CS
• 6+ years in ASIC Physical Design from RTL‑to‑GDSII in either 7nm, 14/16nm, 20nm, or 28nm
• Block Design using EDA tools (examples: Cadence, Mentor Graphics, Synopsys, or others) including synthesis, equivalency verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, and ECO
• Deep understanding of sign‑off activities (timing, ir/em, physical verification)

• Experience in mentoring, leading, or managing more junior engineers
• Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or others) to develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification and ECO
• 4+ years in integrating IP and ability to specify and drive IP requirements in the physical domain
• Thorough knowledge of device physics, custom/semi‑custom implementation techniques
• Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics etc.
• Experience in extraction of design parameters, QOR metrics, and analyzing trends

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

USA, CA, Cupertino – $ – $ USD annually
USA, TX, Austin – $ – $ USD annually

Our inclusive culture empowers Amazonians to deliver the best results for our customers.

Company - Annapurna Labs (U.S.) Inc.

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