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CPU Core Physical Design Engineer

Job in Folsom, Sacramento County, California, 95630, USA
Listing for: Intel
Full Time position
Listed on 2026-06-05
Job specializations:
  • Engineering
    Systems Engineer, Electrical Engineering
Salary/Wage Range or Industry Benchmark: 125000 - 150000 USD Yearly USD 125000.00 150000.00 YEAR
Job Description & How to Apply Below
Position: CPU Core  Physical Design Engineer

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud‑to‑edge technology is at the heart of countless innovations. With a career at Intel, you’ll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life.

Join us and help make the future more wonderful for everyone.

We’re looking for a motivated and talented engineer to join the US CPU design team. In this role you will be critical to the development of next generation CPUs designed to power the AI revolution.

The CPU Physical Design Engineer
  • Performs physical design implementation of custom CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
  • Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
  • Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams.
  • Possesses CPU‑specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.
  • Works intimately with industry EDA vendors to build and enhance tool capabilities to design a high‑speed, low‑power synthesizable CPU.
  • Optimizes CPU design to improve product level parameters such as power, frequency, and area. Participates in the development and improvement of physical design methodologies and flow automation.
Highly Qualified Candidates Will Possess The Following Behavioral Traits
  • Strong problem solving.
  • Tolerance of ambiguity.
Qualifications

Minimum Qualifications
  • The candidate must possess a bachelor’s degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 2+ years of experience OR master’s degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 1+ years of experience.
  • 1+ years of experience in VLSI circuit design and synthesis.
  • 1+ years of experience in static timing analysis.
  • 1+ years of experience in low power design.
Preferred Qualifications
  • Experience in x86 CPU architecture.
  • Tcl/Perl/Python programming.
Benefits

Our total rewards package goes above and beyond just a paycheck. Whether you’re looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals.

Annual Salary Range for jobs which could be performed in the US: $ -  USD.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Location

Primary: US, California, Folsom

Business Group

Silicon and Platform Engineering Group (SPE):
Deliver breakthrough silicon and platform solutions that deliver industry‑leading products today while also defining the next generation of computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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