Mixed Signal Logic Design Engineer

Job Details

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or high‑speed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.

Minimum Qualifications

• Bachelor's with 4+ years of experience or master's with 3+ years of experience or PhD with 1+ year of experience in Computer Science, Computer Engineering, Electrical Engineering, or related technical discipline.

2+ years of experience with the following technical skills:

• Proficiency in RTL design and coding using System Verilog and Verilog.
• Expertise in mixed signal fundamentals, low‑power design using UPF, and clock gating.
• Deep understanding of digital and analog design principles, clock domain crossing, and power‑performance tradeoffs.
• Experience with hardware simulation tools and methodologies (VCS/Verdi) and familiarity with IP environment and configuration management tools.
• Experience with Front End design tools for lint, CDC, RDC, voltage domain crossings, synthesis, low power design.

This position is not eligible for Intel immigration sponsorship.

• Demonstrated ability to debug complex logic designs, speed paths, and validate system‑level functionality.
• Ability to collaborate across diverse teams, mentor junior engineers, and contribute to a dynamic team environment.
• Strong problem‑solving skills, disciplined execution, and a proactive mindset.
• DDR design domain knowledge with good hold on DFI/DDR/LPDDR protocols.
• Experience with VSCode, Git Hub Copilot, or other AI; exposed to formal property verification and Git version control.
• Ability to drive an optimal solution between analog and digital designs.
• Familiarity with pre‑silicon and post‑silicon validation.

Experienced Hire

Shift 1 (United States of America)

US, California, Folsom

US, California, San Jose; US, California, Santa Clara

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars:
Product Enablement (IP, tools, and methodologies), Custom ASIC, and Foundry Enablement. The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

The role offers a total compensation package that includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. The annual salary range for US locations is $ - $ USD.

This role requires an on‑site presence. Job posting details such as work model, location, or time type are subject to change.

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