Post Doctoral Fellow; PREP

General Description

This position is part of the National Institute of Standards (NIST) Professional Research Experience (PREP) program. NIST recognizes that its research staff may wish to collaborate with researchers at academic institutions on specific projects of mutual interest and thus requires that such institutions be the recipient of a PREP award. The PREP program requires staff from a wide range of backgrounds to work on scientific research in many areas.

Employees in this position will perform technical work that underpins the scientific research of the collaboration.

Reliability testing of wide bandgap semiconductor power devices

U.S. Citizen is preferred.

Reliability is the most critical factor in power electronics. As systems face increasing electrical, thermal, and mechanical stress, individual components degrade, causing untimely failures. Rapid electrification and the aging grid infrastructure can only be addressed if the underlying power electronic components are reliable. Current testing standards for existing silicon-based electronics fail to accurately capture the performance and failure mechanisms of newer wide bandgap (WBG) semiconductor materials like SiC and GaN.

Advantages of WBGs—such as higher efficiency, small footprint, higher power—can be overshadows by reliability issues that standard silicon-based test methods cannot detect. Without accurate test protocols to evaluate reliability of emerging WBG semiconductors, manufacturers will face higher costs and will adopt them at lower rates. This project will aim to adopt a three-pillar measurement approach that can overcome the limitations of the current test protocols.

This work will address electrical, material and mechanical degradation via real‑time characterization methods. Pillar one is focused on building a dynamic testing apparatus for stress‑testing of power devices under high voltage swings to capture the transient behaviors of internal resistance and threshold voltage hysteresis that occur in devices only when actively switching in a circuit. The second pillar will address dielectric breakdown at interfaces using AC gate stress testing under realistic loads.

Finally, pillar three will employ an advanced Power Cycling Test (PCT) with microsecond resolution internal temperature measurements in order to correlate electrical load stressors with thermal stress and mechanical packaging failures. Our focus will be on “active load” simulations rather than passive testing, therefore giving us and the industry high‑quality data that is highly desired.

• Build and fully characterize one or more dynamic testing circuits for stress‑testing of power devices, such as GaN HEMTs, under voltage or current transients.
• Evaluate dielectric breakdown at interfaces using AC gate stress testing under realistic loads.
• Perform advanced power cycling measurements to evaluate thermal stress and packaging failures.
• Present results at internal and external meetings and conferences.
• Write peer‑reviewed journal articles on novel and important research findings.

• A master's or a Ph.D. degree in Electrical or Mechanical Engineering, or a related field.
• 3 years of relevant experience, including graduate research work.
• Proficient in PCB layout and circuit simulations and modeling.
• Familiarity with data analysis techniques and mathematical computations using programming tools such as Python or MATLAB.
• A strong desire to collaborate with other researchers and be involved on various related projects.
• Strong oral and written communication skills.

The referenced salary range is $85,000 – $90,000 per year.

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