Senior Design Engineer - MMU & TLB

What You'll be Doing

* Implementation, debugging, and optimization of a high-performance MMU/TLB for a state-of-the-art processor

Skills Required

* Requires 5 to 8 years of experience (bright individuals with lower experience can also apply)

* Experience or background with memory management units, including look-up engines, TLBs, and control

* Good understanding of system architecture, and experience with power/performance tradeoffs

* Design experience with deep submicron technology, specifically low power design techniques

* Verilog / System Verilog / Synthesis / STA / CDC / Lint experience

* Knowledge of programming and scripting languages a plus