FPGA Design Engineer; Level 3 or - R10229306

Relocation assistance:
None. Clearance required to start:
No, but must be able to obtain and maintain a DoD Top Secret clearance. Travel:
Yes, approximately 10% of the time.

Principal / Sr. Principal Digital Design Engineer

Location:

Linthicum, Maryland. Eastern Engineering team.

This role is contingent upon award win with an anticipated start date of June 2026.

• Develop digital logic designs for space applications such as satellite command and control and sensor data processing.
• Design, develop, create and modify digital logic designs implemented with Xilinx and Microsemi FPGA IDEs.
• Simulate and verify FPGA logic designs, compliance requirements, and support validation at the system level.
• Work with members of multi‑functional teams to develop innovative solutions.
• Communicate clearly and effectively with cross‑functional team members.
• Document design and analysis reports as well as test reports.

• Bachelor's in STEM discipline with 5 years of related experience, or a Master’s Degree with 3 years of related experience, or a PhD with 0 years of related experience.
• Experience designing, architecting, and using various FPGAs in processor designs (knowledge of VHDL or other high level language a plus).
• Experience defining and executing development test plans and/or methods.
• Must be a U.S. citizen.
• No clearance required to start, but must have the ability to obtain and maintain a DoD Top Secret clearance.

• Bachelor's in STEM discipline with 8 years of related experience, or a Master’s Degree with 6 years of related experience, or a PhD with 3 years of related experience.
• Digital subsystem, ASIC, FPGA and/or digital board development experience and knowledge essential.
• Candidate must have good communication skills, strong interpersonal skills, and good oral and written presentation skills.
• Must be able to mentor and coach early career Engineers as needed.
• Must be U.S. Citizen.
• Must be able to obtain and maintain Secret or Top‑Secret level security clearance, per business requirements.

• Active DoD Top Secret Clearance.
• Experience translating customer requirements into functional block diagrams that can be realized as FPGAs or other digital logic circuit card assemblies.
• Strong experience with MATLAB and Simulink modeling and programming.
• Develops detailed specifications from high level design goals and performs analysis of the hardware, system environment and design goals to enable selection and implementation of the desired system topology.
• Can clearly present assigned work at program technical reviews, proposals, or other technical meetings.
• Possesses strong interpersonal skills to work effectively within a development team to understand system level inter‑dependencies and design constraints.
• Conduct trade studies, identify and present alternate design options.
• Experience with Systems Engineering principles.

Primary Level Salary Range: $ - $

Secondary Level Salary Range: $ - $

The above salary range represents a general guideline; however Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, company‑paid holidays and paid time off (PTO) for vacation and/or personal business. Employees may be eligible for overtime, shift differential, discretionary bonuses, and long‑term incentives depending on position.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, visit the Northrop Grumman website. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.