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Ultra-Low Latency ASIC Engineer; FPGA​/ASIC

Job in Greater London, London, Greater London, W1B, England, UK
Listing for: Jane Street
Full Time position
Listed on 2026-05-30
Job specializations:
  • Engineering
    Hardware Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 GBP Yearly GBP 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Ultra-Low Latency ASIC Engineer (FPGA/ASIC)
Location: Greater London

Jane Street is seeking an experienced ASIC Engineer in Greater London to design, test, and deploy advanced hardware designs. You'll collaborate with teams in trading, networking, and research infrastructure while contributing to both FPGA and ASIC technologies.

Ideal candidates have over 4 years of experience in RTL design and verification, and expertise in ASIC design using Synopsys or Cadence. You should also be eager to utilize software engineering techniques to enhance the hardware design process.

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