Design Verification; DV Engineer

ITAR Notice

ITAR controlled information. Applicants must be U.S. persons as per 22 CFR 120.62.

You will own functional verification of our custom AI accelerator's digital logic — writing test benches, building verification environments, debugging waveforms, and driving coverage closure. You'll work in System Verilog and UVM with industry‑standard simulators (Synopsys VCS, Cadence Xcelium) and waveform viewers (Synopsys Verdi). Your work ensures that the design is correct before tape‑out — every bug you find in verification is a bug that doesn't cost millions to fix in silicon.

• Build the UVM verification environment for the custom accelerator — develop the testbench architecture, constrained‑random stimulus generators, scoreboards, and coverage models
• Write directed and constrained‑random tests targeting compute pipeline, NOC routing, memory subsystem, and control plane logic
• Debug RTL mismatches using waveform analysis in Verdi/DVE — isolate root causes and file clear bug reports against the design team
• Drive functional coverage closure — define coverage goals, track progress, identify verification holes
• Develop assertion‑based verification (SVA) monitors for protocol compliance (APB, AXI, SPI, JTAG interfaces)
• Validate ISA‑level correctness — ensure the LLVM backend's generated code executes correctly on the RTL design
• Establish regression infrastructure — automated nightly runs, pass/fail reporting, coverage merging

• System Verilog — expert‑level proficiency in both RTL reading and verification constructs (classes, interfaces, constraints, cover groups). This is your primary language.
• UVM — you have built or significantly extended UVM environments and understand agents, sequences, scoreboards, and the factory pattern.
• Logic simulation — hands‑on experience with Synopsys VCS, Cadence Xcelium, or equivalent. You can debug simulation failures efficiently.
• Waveform debugging — skilled with Synopsys Verdi, Cadence Sim Vision, or equivalent, able to trace signal transitions through a multi‑thousand‑line design.
• Verification methodology — you understand coverage‑driven verification, constrained‑random testing, and can build a verification plan that catches real bugs.
• (Optional) SVA assertion writing for protocol and microarchitectural properties
• (Optional) Coverage analysis and closure experience on a tape‑out project
• (Optional) Python or Tcl scripting for regression automation and log parsing
• (Optional) RISC‑V ISA familiarity (our control plane uses RISC‑V)
• (Optional) Experience verifying processor or accelerator designs specifically

Base salary: $180k – $320k USD per year, depending on experience and qualifications. Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Discussed in detail during the interview.

Density

AI sponsors qualified candidates for H‑1B, O‑1, TN, E‑3, and other employment‑based visas, and welcomes applicants on F‑1 OPT and STEM‑OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.

This role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

Density

AI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.