Design Verification Engineer
Job in
San Francisco, San Francisco County, California, 94199, USA
Listed on 2026-06-02
Listing for:
ACL Digital
Full Time
position Listed on 2026-06-02
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer, Test Engineer
Job Description & How to Apply Below
* Develop and maintain UVM-based verification environments
* Verify CPU subsystems and instruction execution
* Implement constrained-random testing
* Integrate Instruction Set Simulators (ISS) with DV environments
* Debug complex functional issues across hardware and testbench
Requirements:
* 5+ years Design Verification experience
* Strong skills in:
* System Verilog
* UVM
* Testbench architecture
* Experience verifying processor or CPU subsystems
Preferred:
* Familiarity with Instruction Set Simulators (Spike or similar)
* Experience with random instruction generators (Sting)
* Knowledge of processor software tool chains
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