Field-Programmable Gate Arrays Engineer

• 5 + years of large high speed FPGA design relevant experience.
• Design Experience using the internal PLL circuits (phase lock loops)
• Experience with design of Embedded Algorithmic Pattern Generator (APG) core & the interface between the APGs and the Pin Electronics I/O
• Good understanding of timing constraints in the FPGA to be able to achieve consistent timing results from build to build

Responsibilities:

• Design the timing generators. The timing generators require fine timing control inside the FPGA.
• Design the signal formatting blocks inside the Test Controller FPGA.
• Design the Embedded Algorithmic Pattern Generator (APG) core. There will be multiple APG cores in the FPGA
• Design the interface between the APGs and the Pin Electronics I/O
• Implement the internal Vector Memory block
• Implement the internal Error Capture RAM (ECR) block and the ECR data transfer block to move the data to the external memory
• Ensure blocks are functional via simulation initially and then on the hardware when available.
• Work with the hardware design team and the software team to assist bring-up and driver development.
• Maintain and update relevant documentation and records as required.