Sr. Physical Design Engineer, Annapurna Labs

Sr. Physical Design Engineer, Annapurna Labs

Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable just recently. Our custom chips, accelerators, and software stacks enable us to tackle technical challenges that have never been seen before, delivering results that help our customers change the world.

Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud‑Scale Machine Learning Acceleration team you’ll be responsible for the design and optimization of hardware in our data centers, including AWS Inferentia and Trainium Systems. We’re looking for an ASIC Physical Design Engineer to help us trail‑blaze new technologies and architectures while ensuring high design quality and making the right trade‑offs.

• Work with RTL/logic designers to drive architectural feasibility studies, exploring power‑performance‑area trade‑offs for physical design closure.
• Drive I/O/Core subsystem/block physical implementation through synthesis, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign‑off.
• Develop physical design methodologies.
• Evaluate 3rd‑party IP and provide recommendations.
• Collaborate and teamwork with other physical design engineers and RTL/Arch teams.

• Experience scripting with Python, Perl, Bash or Power Shell.
• BS + 8 years or MS + 6 years in EE/CS.
• 6+ years in ASIC Physical Design from RTL‑to‑GDSII in either 7nm, 14/16nm, 20nm or 28nm.
• Block design using EDA tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) including synthesis, equivalency verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification and ECO.
• Deep understanding of sign‑off activities (timing, IR/EM, physical verification).

• Experience in mentoring, leading, or managing more junior engineers.
• Expertise using CAD tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) to develop flows for synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop, physical verification and ECO.
• 4+ years in integrating IP and specifying and driving IP requirements in the physical domain.
• Thorough knowledge of device physics, custom/semi‑custom implementation techniques.
• Experience solving physical design challenges across various technologies such as DDR, PCIe, fabrics, etc.
• Experience in extraction of design parameters, QOR metrics and analyzing trends.

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

• Base salary ranges:
  • USA, CA, Cupertino: $ – $ USD annually
  • USA, TX, Austin: $ – $ USD annually
• Amazon package includes sign‑on payments and restricted stock units (RSUs).
• Comprehensive benefits: health insurance (medical, dental, vision, prescription), Basic Life & AD&D insurance, optional Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage, 401(k) matching, paid time off, parental leave.