ASIC​/RTL Design Engineer

Responsibilities

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and AMD internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected to contribute in all aspects of SoC design including:
Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ARM cores and other I/O standard interfaces.

• Strong communication and documentation skills
• Good organizational, time management and multitasking coding, debugging/verification, and supporting synthesis and timing closure
• Working knowledge of skills, Strong initiative and discipline to follow-through, Technical leadership