Lead Hardware System Architect

Lead Hardware System Architect

Bolt Graphics Sunnyvale, California, United States Information Technology

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

• Be Fearless: Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
• Educate Your Ego: Selflessly collaborate towards our shared purpose.

As the Lead Hardware System Architect, you will own the end-to-end hardware development lifecycle for our next-generation graphics compute platforms, high-performance GPU servers, and ultra-high-speed PCIe graphics form factors. You will act as the technical bridge between advanced graphics silicon packaging and system-level deployment, driving physical architecture, functional partitioning, and high-speed fabric optimization for massive graphics workloads and real-time rendering infrastructure.

In this role, you will not just oversee board layouts; you will define the physical topologies that enable cutting-edge graphics compute scaling. You will serve as the ultimate technical escalation point for our global JDM/ODM engineering partners, steering them through complex bring-up, signal integrity boundaries, and root-cause failure analysis to deliver flawless graphics hardware on schedule.

• Architect the Platform: Drive system-level architectural trade-offs, balancing high-performance GPU silicon package constraints, high-speed routing density, thermal mechanics, and ultra-high-density power delivery networks (PDNs).
• Own High-Speed Topologies: Design and optimize complex PCB topologies utilizing PCIe Gen 5/Gen 6 (CEM specifications) and proprietary/consortium scale-up interconnect fabrics designed for parallel compute and graphics scaling (e.g., NVLink, Infinity Fabric, UA Link).
• Systemic Co-Design: Collaborate with Silicon, Signal/Power Integrity (SI/PI), and Thermal/Mechanical teams to define robust board stack-ups, low-loss material selection, and multi-phase power zones handling massive transient loads from modern graphics processors.
• Management Integration: Ensure seamless integration of out-of-band telemetry and management infrastructure, designing physical routing for Baseboard Management Controllers (BMCs), SPI, and I2C/SMBus topologies.

• Lead Technical Enablement: Serve as the primary technical authority interfacing with international JDM/ODM layout and hardware engineering teams.
• Triage & Failure Analysis: Lead complex hardware debug, component-level troubleshooting, and failure analysis (FA) during early-phase platform bring-up and validation of graphics compute hardware.
• DFX & Execution Governance: Enforce rigorous design reviews and strict compliance with DFX (Manufacturing, Assembly, Test, and Automation) standards to ensure high-yield transitions from EVT/DVT to High-Volume Manufacturing (HVM).

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
• Experience: 8+ years of hardware design experience, with a proven track record of shipping high-performance graphics hardware, GPU motherboards, or high-density parallel compute accelerator boards.
• Fabric & Bus Expertise: Deep, hands-on experience designing with PCIe Gen 5/6 and high-speed serdes (112G/224G PAM4 architectures). Familiarity with CXL or scalable interconnect fabrics is highly desired.
• Advanced Power & SI/PI: Strong understanding of high-frequency PCB layout constraints, via optimization, and power delivery networks capable of handling extreme di/dt step loads inherent to dynamic graphics workloads.
• Hardware Tooling: Proficiency…