Senior ASIC Design Engineer, Google Cloud

Location

Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or System Verilog.

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with three or more SoC projects/cycles.
• Familiarity with the full ASIC flow (DFT, synthesis, PnR), Ser Des behavior, and scripting (Python, Tcl, or Perl) to drive technical execution.
• Expert knowledge of NoC/Memory architecture, flow control, and performance tuning.
• Proven ability to lead cross‑functional efforts with software and system hardware teams, from initial library RTL development through to silicon bring‑up.
• Advanced RTL design skills with mastery of multi‑clock domains, timing closure, datapath optimization, and hardware/firmware partitioning.

As a Design Engineer, you will architect and implement SoC‑level RTL for next‑generation data center accelerators. You will design high‑performance subsystems, build the foundational SoC infrastructure—including clocking, reset, error handling, and chip management—to power our silicon. In this highly cross‑functional role, you will have a “big picture” view of the product life‑cycle from concept to production, requiring close collaboration with software and hardware teams to deliver accelerators.

• Drive the complete RTL life‑cycle from initial microarchitecture, coding, and documentation to sign‑off readiness (lint, CDC, synthesis) for high‑performance designs meeting strict PPA targets and quality guidelines.
• Collaborate with system architects to align on chip‑level bandwidth, latency, and power objectives, and partner with the Verification and Physical Design teams to define test plans and achieve timing closure.
• Identify test requirements, define methodology/tools, and execute testing of silicon systems; drive protocol resolution and lead post‑silicon bring‑up to validate link integrity and subsystem performance.
• Influence designs to enhance testing, validation, and debugging capabilities, while establishing third‑party IP requirements and driving the selection process.
• Develop and maintain policies, processes, procedures, methods, and documentation for silicon deliverables to enhance efficiency, productivity, and project sustainability.

US: $163,000 - $237,000 (USD) + 15% bonus target + bonus + equity + benefits.

Google is a proud equal‑opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy, or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law.