Hardware Architect - Cognitive Robotics; human

This is where Artificial Intelligence comes to life. The Hardware Department designs, constructs, and optimizes all physical components of our cognitive robots. As NEURA scales from prototype to production of five million robots, the decisions made at the architecture level today will shape the platform for years to come. The Hardware Architect is the person who makes those decisions — with the authority to define the blueprint and the accountability to make it work in the real world.

You define the hardware blueprint for the world's most advanced cognitive robots.

NEURA's humanoid robot is a deeply complex cyber-physical system: distributed computing, high-density power electronics, a body-area sensor network, real-time actuation control, and a cognitive AI stack — all packed into a human-scale form factor and designed for mass production. The Hardware Architect owns the overall hardware system architecture, translates product requirements into physical design constraints, and ensures that every sub-system — from PCBAs to cabling to compute modules — fits coherently into a scalable, manufacturable whole.

• Hardware system architecture: Define and maintain the top-level hardware architecture of the robot platform — compute topology (SoCs, MCUs, edge AI accelerators), power architecture (bus voltages, distribution, protection), communication backbone (Ether
  
  CAT, CAN-FD, Ethernet, Ser Des), and sensing architecture (sensor selection, placement, interface strategy).

• Requirements & partitioning: Translate product, performance, and safety requirements into hardware requirements; partition functionality across electronics, embedded software, and mechanical subsystems; manage technical interfaces between all hardware disciplines.

• Architecture governance: Lead hardware architecture reviews; define and enforce hardware design standards, interface control documents, and design rules across the electronics, firmware, and mechanical teams.

• Technology selection: Evaluate and select key platform components — compute SoCs, power management ICs, communication controllers, sensor ICs — balancing performance, availability, NRE cost, and long-term scalability.

• Cross-disciplinary integration: Serve as the primary technical interface between the hardware team and software/AI architecture teams; ensure the hardware platform exposes the right capabilities (memory bandwidth, I/O, compute) to meet AI inference and real-time control requirements.

• DFM and scalability: Ensure architectural decisions are compatible with high-volume manufacturing; drive design-for-reliability, design-for-testability (DFT), and design-for-cost principles from day one.

• Technical mentorship: Provide technical guidance and mentorship to senior electronics, firmware, and system engineers; support hiring and team growth in the hardware domain.

A rare combination: system-level thinker and hands-on hardware expert.

You are a senior hardware engineer or architect who has seen the full lifecycle of a complex embedded hardware product — from architecture concept through mass production — and who understands what it takes to get architecture right at each stage. You lead by technical authority, not organizational position, and you thrive in environments where the architecture is still being shaped.

• Master's degree in Electrical Engineering, Computer Engineering, Mechatronics, or a closely related field;
  PhD is a plus but not required.

• 8+ years of professional experience in hardware development for complex embedded or cyber-physical systems, with at least 3 years in a hardware architecture, lead engineer, or staff engineer role.

• Proven track record of defining and delivering multi-disciplinary hardware system architectures — from concept through EVT/DVT and into production — for products combining high-speed compute, power electronics, and real-time sensing.

• Deep understanding of embedded compute platforms (ARM Cortex-A/M, NVIDIA Jetson class, FPGA/eFPGA) and the trade-offs between centralized and distributed compute topologies.

• Strong command of power system architecture: multi-rail SMPS design, battery/BMS…