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PMU Design Verification Engineer; m​/f​/d

in Nabern, Baden-Wurttemberg, Deutschland
Unternehmen: Apple
Vollzeit position
Verfasst am 2026-01-19
Berufliche Spezialisierung:
  • Ingenieur
    Software-Ingenieur, Elektronikingenieur, Testingenieur, Systemingenieur
Stellenbeschreibung
Stellenbezeichnung: PMU Design Verification Engineer (m/f/d)
Location: Nabern

Overview

At Apple, we work every single day to craft products that enrich people’s lives. We are looking for a results-oriented and highly committed experienced Design Verification Engineer to join our team in Nabern, near Stuttgart. As a member of our multifaceted group, you will have the outstanding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day.

The responsibilities involve all phases of pre-silicon verification including establishing design verification methodology and test-plan development, as well as verification environment development such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Responsibilities
  • You will develop verification plans in coordination with design leads and architects.
  • You’ll be responsible for building and maintaining verification test bench components and environments.
  • Generate directed and constrained random tests.
  • Run simulations and debug design and environment issues.
  • Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.
  • Craft automated verification flows for block and chip level verification.
  • Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (System Verilog/UVM), and logic simulators to verify complex designs.
  • Work with other block and core level engineers to ensure a flawless verification flow.
Minimum Qualifications
  • Bachelors in EE or related field, or equivalent work experience
  • Excellent communication and interpersonal skills, combined with the ability to collaborate
  • Ability to work well on a team, take ownership and motivate self and others
  • Fluent English skills
Preferred Qualifications
  • Sophisticated knowledge of System Verilog and UVM
  • Experience developing scalable and portable test-benches
  • Experience with constrained random verification environments
  • Experience defining coverage space, writing coverage model, analyzing results
  • Experience with Assertion Based Verification
  • Good Knowledge of Object Oriented Programming
  • Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
  • Experience with Python, Perl or TCL
  • Good understanding of digital design and basic knowledge of mixed signal verification

At Apple, we’re not all the same. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

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