Sr Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

We are seeking an exceptional Senior Principal Engineer to provide technical leadership on some of the industry's most challenging silicon development programs. In this role, you will apply deep expertise in silicon implementation and advanced EDA methodologies to solve problems and deliver results. You will work directly with strategic customers and internal Cadence teams to develop, deploy, and demonstrate innovative methodologies for advanced-node designs.

This is a hands‑on technical leadership role. The successful candidate will combine outstanding semiconductor engineering expertise with the ability to influence lead a team of implementation engineers and technically contribute to architecture, methodology, tool development, and customer strategy.

• Provide technical leadership for complex, high‑visibility silicon programs, Synthesis/Netlist through physical implementation, signoff, and tapeout.
• Develop and deploy advanced methodologies for achieving aggressive power, performance, and area (PPA) objectives.
• Work closely within the PSG engineering team to understand design implementation challenges and translate them into practical solutions.
• Collaborate directly with Cadence R&D to identify product gaps, influence tool development, and drive enhancements required for advanced silicon designs.
• Drive technical innovation across physical design, timing, power, signal integrity, physical verification, and signoff with the PSG European team
• Evaluate and introduce new Cadence technologies, methodologies, and IP into customer design flows.
• Lead technical investigations involving difficult silicon failures, performance limitations, convergence challenges, or methodology issues.
• Establish reusable methodologies and best practices that can be deployed across multiple customers and technology nodes.
• Mentor and develop our implementation engineers, serving as a technical authority within the PSG EMEA (Europe) organisation.
• Represent Cadence as a technical thought leader with strategic customers, partners, and the wider semiconductor ecosystem.
• Present technical results and innovations to senior leadership, customers, industry forums, and engineering communities.
• Assist in the preparation of pre‑sales support information and effort estimation with the Design Engineering Director and Sales team

• Advanced-node digital implementation
• RTL-to-GDSII flows
• Physical design and optimisation
• Timing closure and signoff
• Power optimisation and analysis
• Signal integrity and electromigration
• SoC integration and hierarchical implementation within a layout team
• IP integration and reuse
• Process/design technology co‑optimization (DTCO)
• Advanced packaging
• Automation and methodology development including AI acceleration.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related…