Senior ASIC Design Lead -Speed DSP & RF Chips

Cesium Astro is seeking a Principal ASIC Design Engineer – Chip Lead in its Jariet Technologies group in California. You will drive cradle-to-grave high-speed mixed-signal/DSP chip projects, from architecture through production.

The role demands deep RTL/System Verilog expertise, verification using UVM/VMM/SPECMAN, and collaboration with frontend/backend teams to meet demanding performance, power, and timing goals. A Master’s degree and 10+ years' experience are required.

This role, Senior ASIC Design Lead for High-Speed DSP & RF Chips at Cesiumastro, could be your next opportunity.

Learn more about the Senior ASIC Design Lead for High-Speed DSP & RF Chips role in the description above.

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