Senior Engineering Professional

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a seasoned engineering professional with a passion for tackling complex SoC challenges. With 12+ years' experience, you thrive in dynamic environments and excel at leading multidisciplinary teams through the intricacies of RTL design and signoff. You possess deep expertise in RTL methodologies, static verification, and timing analysis, and you’re driven to deliver robust, high-quality solutions that enable customer success.

Your collaborative spirit, strategic mindset, and attention to detail allow you to translate customer requirements into innovative design flows. You stay ahead of technological trends, continuously learning new tools and techniques, and you’re eager to mentor others in best practices for design and verification. You value diversity and inclusion, recognizing that varied perspectives fuel innovation. Your communication skills empower you to bridge gaps across teams, stakeholders, and customers, ensuring alignment and clarity.

You take pride in your ability to solve technical problems efficiently, make informed decisions under pressure, and deliver results that exceed expectations. Above all, you are motivated by the opportunity to shape the future of smart technologies and contribute to projects that impact industries worldwide.

• Partnering with Synopsys customers to define RTL signoff and design scopes, ensuring alignment with project objectives.
• Analyzing design complexity and requirements to propose optimal resource allocation for successful project delivery.
• Leading engineering teams in executing pre-silicon static verification activities on IPs and subsystems.
• Developing and refining timing constraints for synthesis and timing, based on design architecture and requirements.
• Collaborating with peers to enhance methodologies, driving improvements in execution efficiency and project quality.
• Adopting and mastering new RTL design and static verification tools/methodologies using Synopsys products for customer enablement.
• Working cross-functionally with Business Unit Application Engineers and Sales to broaden and deploy tool and IP solutions.
• Establishing robust flows and methodologies to enable rapid setup for RTL quality checks, synthesis, and formality.
• Training team members on advanced design concepts and root-cause analysis to foster continuous learning and growth.

• Accelerating customer success by delivering reliable RTL design and signoff solutions for challenging SoC projects.
• Enabling startups, commercial enterprises, and government agencies to achieve first-time-right silicon implementations.
• Driving adoption of innovative Synopsys technologies and methodologies across diverse customer segments.
• Enhancing team capabilities through mentorship and knowledge sharing, fostering a culture of technical excellence.
• Improving project delivery timelines and quality by optimizing verification flows and resource utilization.
• Contributing to the evolution of industry-leading chip design practices and standards.
• Strengthening Synopsys’ reputation as a trusted partner for cutting-edge semiconductor solutions.

• B.E/B. Tech/M.E/M. Tech in electronics or a related field.
• Minimum of 12+ years’ experience in RTL design and verification, with a proven track record of technical leadership.
• Expertise in LINT, CDC, RDC checks, and static verification methodologies.
• Strong background in setting up flows and deploying RTL signoff tools for rapid project initiation.
• Advanced skills in debugging, diagnosing violations, and resolving complex design issues.
• Proficiency in developing and validating timing constraints; experience with preliminary synthesis and area estimation.
• Demonstrated ability to lead teams through the RTL signoff…