Principal Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a visionary and highly accomplished digital design and verification engineer with over 15 years of impactful experience in ASIC development, large-scale system validation, and hardware emulation. As a Principal Engineer, you are recognized for your technical leadership, strategic thinking, and exceptional ability to architect, model, and validate complex mixed-signal SoC systems. Your expertise spans advanced hardware emulation platforms such as Zebu and HAPS, and you have a proven track record of building and optimizing integrated PHY platforms, as well as back-to-back environments on hardware.

You bring a deep understanding of digital signal processing, high-speed serializer/deserializer (Ser Des) architectures, and signal PHY development. Your experience includes leading multi-disciplinary teams, driving technical roadmaps, and mentoring engineers to deliver best-in-class solutions for protocols like PCIE, Ethernet, and USB.

Your strong communication skills and collaborative approach enable you to bridge cross-functional teams and engage effectively with customers and stakeholders. You thrive on solving the toughest technical challenges, setting new benchmarks for design quality, and guiding products from concept to successful deployment. You are committed to fostering innovation, inclusivity, and continuous learning within your team, and you are eager to drive Synopsys’ next-generation silicon architectures to new heights.

• Providing technical leadership and architectural direction for the design and emulation of advanced mixed-signal SoCs, including next-generation Ser Des PHY products.
• Driving the development and integration of hardware emulation strategies on FPGA platforms (Zebu, HAPS).
• Orchestrating the build and validation of system-level prototypes for industry-leading protocols (PCIE, Ethernet, USB, etc.), ensuring seamless integration with PHY builds.
• Guiding the creation and optimization of verification environments using UVM and System Verilog, overseeing testbench and VIP integration for complex architectures.
• Leading automation initiatives and workflow enhancements through advanced scripting in Shell, Perl, Python, and C++.
• Mentoring and coaching engineering teams, fostering technical excellence and knowledge sharing across the organization.
• Collaborating with cross-functional groups and customers to resolve challenges, ensure design quality, and meet aggressive project milestones.
• Driving continuous improvement in functional and performance testing on hardware and test-chips, and leading architectural refinements based on analysis.

• Set the strategic technical direction for flagship silicon IP products, influencing industry standards and Synopsys’ product roadmap.
• Accelerate product innovation and time-to-market by establishing best practices in emulation, validation, and system integration.
• Enhance product differentiation, reliability, and performance—delivering measurable value to global customers.
• Drive cross-team synergy, technical mentorship, and a culture of continuous learning and inclusivity.
• Elevate Synopsys’ reputation as a leader in advanced Ser Des and PHY solutions for high-performance SoCs.
• Directly impact customer success by providing expert guidance, technical support, and innovative solutions.
• Champion diversity and inclusion, ensuring a respectful and opportunity-rich workplace for all team members.

• 15+ years of experience in ASIC design, verification, system validation, and technical leadership roles.
• Recognized expertise with hardware emulation platforms (Zebu, HAPS) and FPGA-based prototyping for signal PHY and back-to-back systems.
• In-depth knowledge of system-level validation for high-speed…