ASIC Digital Verification Engineer

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are a passionate and highly skilled ASIC Digital Verification Engineer seeking to make a meaningful contribution in a collaborative, global environment. With a strong foundation in electrical or computer engineering, you possess a keen eye for detail, a methodical approach to problem‑solving, and a drive to deliver reliable, high‑performance IP solutions for memory interfaces. Your expertise in Verilog, System Verilog, and digital design flows is complemented by your proficiency in scripting languages, enabling you to automate and optimize verification processes for maximum efficiency.

You thrive on tackling complex challenges and are adept at debugging intricate RTL models. Your ability to design comprehensive testplans and robust testbench infrastructure ensures the highest standards of functional coverage and product reliability. You are motivated by continuous learning, staying up‑to‑date with emerging technologies such as virtual prototyping and emulation, and you proactively seek out opportunities to improve team processes and outcomes.

As a senior staff engineer, you are a natural mentor, eager to share your knowledge and expertise with junior engineers, fostering a culture of growth and innovation. Your communication and organizational skills allow you to collaborate effectively with architecture and implementation teams, contributing to technical reviews and driving consensus on best practices. You are committed to excellence, integrity, and inclusivity, making you a valued member of the Synopsys Solutions Group.

• Developing detailed testplans and functional coverage models to ensure robust verification of training firmware on RTL PHY models.
• Implementing scalable testbench infrastructure and creating comprehensive test cases, including success path, corner case, and negative scenarios.
• Collaborating with architecture and implementation teams through technical reviews, contributing insights to enhance product quality and performance.
• Solving complex, abstract verification challenges with strong debugging skills and analytical thinking.
• Researching and integrating emerging technologies in virtual prototyping and emulation to drive continuous improvement in team efficiency and product quality.
• Mentoring junior engineers, fostering skill development, and cultivating leadership capabilities within the team.

• Accelerating the delivery of high‑performance, reliable IP solutions for memory interfaces, directly influencing next‑generation silicon products.
• Elevating verification standards across the Solutions Group through innovative testplan design and coverage analysis.
• Driving improvements in productivity, performance, and throughput by developing and implementing advanced verification solutions.
• Ensuring seamless integration and verification of firmware and hardware, enhancing the functionality and reliability of Synopsys products.
• Contributing to the adoption of cutting‑edge methodologies like assertion verification and protocol‑oriented performance analysis.
• Empowering team growth and knowledge sharing by mentoring peers and junior engineers, building a resilient and forward‑thinking engineering culture.

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, with 5+ years of relevant experience.
• Expertise in Verilog, System Verilog, and the IC design flow, including simulation and waveform debugging tools.
• Proficiency in scripting languages such as Python, Perl, Bash, and experience with makefiles; co‑simulation experience is a strong asset.
• Strong understanding of digital logic principles and verification methodologies, including UVM (Universal Verification Methodology).
• Experience with DDR interface…