Principal Verification Engineer

Position: Principal Verification Engineer (f/m/div)

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Are you a passionate engineer who wants to join a verification team using leading-edge tools and methodologies? Do you want to be part of the growth of our Design Center in Bristol? Are you fascinated by the future of mobility and want to play a key role at the #1 semiconductor partner in the fast-changing world of automotive? Then our team in Bristol is waiting for you!

Join us as a Principal Verification Engineer and don’t miss this opportunity to join Infineon’s success story.

As a Principal Verification Engineer, you will play a critical role in developing and maintaining System Verilog - UVM test benches, solving complex problems, and leading the development of new SV UVM verification components. Your responsibilities will also include understanding and modifying Specman-e test benches, debugging failing test cases, and defining a functional coverage model. Additionally, you will contribute to enhancing the verification strategy and architecture of IP test benches, ensuring test bench quality, and meeting sign-off targets.

In your new role, you will:

• Be responsible for developing System Verilog - UVM testbench and solve potentially complex problems related to test bench development
• Be responsible and lead developing of new SV UVM verification components
• Able to understand and modify Specman-e test benches
• Debug failing test cases to root cause
• Be responsible for defining and writing a functional coverage model
• Participate in reviews to ensure the test bench meets quality and is complete
• Contribute to verification perspective in Design and Concept meetings.
• Ensure the test bench meets sign-off targets, including coverage, functional safety, and test bench qualification.
• Develop a deep understanding of complex IPs and take end-to-end ownership of the verification of these sub-blocks;
• Proactively help increase the efficiency of verification activities and mitigate risks early.
• Contribute to enhancing the Verification strategy and architecture of IP test benches.

You put your team player spirit into your everyday work and are also looking forward to work with different people in a stimulating environment. Your proactive personality allied with your excellent communication skills allow you to solve problems in an effective way. You have a detail-oriented mindset and the job specific skillset that helps you increase the efficiency of the verification activities.

Furthermore, you are personally committed to our customers’ concerns and strive to constantly and consistently exceed their expectations.

You are best equipped for this role if you have:

• A Bachelor's degree in Electrical/Electronic Engineering or equivalent degree
• At least 10 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM;
  Prior knowledge in Specman-e is desirable
• Advanced knowledge in UVM and SVAs, System Verilog
• Experience with Verification platform and framework development
• Proven experience of ownership of IP verification including delivering to metric targets
• Capability to understand complex Design specification, derive features and test bench architectures from concept
• Capability to use industry-standard EDA tools
• Good time management skills and the ability to deliver to high quality requirements under pressure
• Aptitude for clear communication of issues and progress
• A safety-first approach with ability to pay close attention to detail
• Ability to communicate clearly in English

You may also have:

• Knowledge of functional safety and verification
• Knowledge of scripting languages
• Knowledge in the following tools/systems
• Linting tools: PC Lint or equivalent
• Revision control systems:
  Clearcase, SVN, Git, or equivalent

Please send us your CV in English.

Contact:

Luis Oliveira, Linked In

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