Senior Verification Engineer

Senior Verification Engineer (f/m/div)

Infineon Technologies invites applications for the role of Senior Verification Engineer on our R&D team.

• Contribute to the development of System Verilog‑UVM test benches.
• Assist in debugging failing test cases and identifying root causes.
• Help define functional coverage models and ensure coverage goals are met.
• Collaborate in team reviews, design discussions, and process improvements.
• Support test bench quality and sign‑off targets, including coverage metrics and functional safety requirements.

• A bachelor’s degree in Electrical/Electronic Engineering or a related field.
• 1‑2 years of verification engineering experience, including hands‑on System Verilog‑UVM exposure.
• Strong understanding of verification concepts and System Verilog fundamentals.
• Enthusiastic about learning industry‑standard methodologies such as UVM.
• Knowledge of debugging workflows and willingness to learn debugging tools.
• Strong problem‑solving and collaborative skills with effective time management.
• Fluency in English (mandatory).

Send your CV in English to Rita Costa on Linked In.

Infineon values diversity and inclusion. All applicants receive equal opportunity based on experience and skills.