Senior Design Verification Engineer

An exciting opportunity has just opened for a Senior Design Verification Engineer to join a cutting-edge team in Cambridge, UK, driving innovation in next‑gen semiconductor projects

Senior Design Verification Engineer

Cambridge, UK

Permanent

Negotiable (depending on qualifications and experience)

As a Senior Design Verification Engineer, you will apply industrial‑strength verification to both system‑ and block‑level designs, including RISC‑V cores, OTBN (cryptographic CPU), AES accelerators, and peripherals like USB, I2C, and SPI.

• Design, implement, and debug block/system‑level tests and test benches using System Verilog and UVM
• Develop test and coverage plans for new and updated designs
• Triage and debug nightly regressions
• Review contributions to open‑source projects
• Enhance test and CI infrastructure
• Collaborate on academic/industry publications
• Stay current with verification best practices and introduce improvements

• 5+ years industry experience in design verification
• Strong System Verilog and UVM expertise
• Experience across the full verification cycle (planning to tape‑out)
• Able to provide estimates and coordinate with project managers
• Comfortable in multidisciplinary, multi‑organisation teams
• Familiar with Git and code review tools (Git Hub, Git Lab, Gerrit)
• Programming in C and/or Python for tests and automation
• Undergraduate degree in a technical discipline or equivalent

• Experience with multiple hardware block types
• Knowledge of security countermeasures (fault injection, side‑channel attacks)
• Experience with RISC‑V ISA or other instruction sets
• Familiarity with formal verification tools (e.g., Jasper Gold)

• 25 days annual leave + 8 bank holidays
• Employer pension contribution
• Private medical insurance, income protection, critical illness and life cover
• Opportunities to attend industry conferences and training

If you could be interested for this position, please get in touch and share your CV with me