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Senior Firmware Developer

Job in City of Edinburgh, Edinburgh, City of Edinburgh Area, EH1, Scotland, UK
Listing for: Ten Live Group
Full Time position
Listed on 2025-12-04
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Job Description & How to Apply Below
Location: City of Edinburgh

1 day ago Be among the first 25 applicants

Direct message the job poster from Ten Live Group

International Talent Acquisition Manager, Ten Live Group, Global Resource Solutions, a TOP 90 companies in Scotland/Business Mentor Chamber of…

Our client, an international player in the optical communications sector, is recruiting a Senior Firmware Developer.

Are you highly experienced in the design of FPGA IP cores or sub-systems? Can you competently design FPGA architectures from a technical specification and design with AMD/Intel FPGA and CPLD devices? Are you experienced in the following:
Using VHDL/Verilog HDL languages for FPGA design? Implementing high speed, multi-frequency clocking architectures? Designing (code entry to timing analysis) using Intel and/or Xilinx FPGA tool sets? Designing for high-speed optical interfaces? Designing for high-speed SERDES interfaces (up to 28G/56G)?

If the above are your areas of expertise, you fully expect a salary that reflects your technical know-how and would be motivated by an exciting and highly inclusive business culture, please get in touch by sending us your CV

Other Key Role Requirements

  • Qualified to degree level in Electronic Engineering, Computer Science or equivalent discipline
  • Ability to comply with the UK GOV National Security Vetting Procedures (see link below)

P.S.

The role comes with a highly competitive salary + package: optional pre-tax pension contribution, 28 days paid holiday (plus statutory holidays), performance-related bonus scheme, fantastic working environment.

Qualifications
  • • Qualified to degree level in Electronic Engineering, Computer Science or equivalent discipline
  • • Ability to comply with the UK GOV National Security Vetting Procedures (see link below)
Responsibility Summary

Responsibilities are centred on designing FPGA IP cores and sub-systems, and related high-speed architectures, clocking, and interfaces in FPGA devices; using VHDL/Verilog; timing analysis; and integration with high-speed optical and SERDES interfaces as described above.

Benefits

The role offers a highly competitive salary and package, including optional pre-tax pension contribution, 28 days of paid holiday (plus statutory holidays), and a performance-related bonus scheme.

Apply BELOW

Position Requirements
10+ Years work experience
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