Mixed-Signal Verification Engineer – AMS​/SerDes Systems; EU Locations

Mixed-Signal Verification Engineer – AMS / Ser Des Systems (Multiple EU Locations)

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About the Role

We are looking for a resourceful Mixed-Signal Verification Engineer to contribute to the verification of advanced analog/mixed-signal subsystems, including high-speed communication interfaces. This role is ideal for someone who enjoys solving challenging AMS verification problems, pushing methodology innovation, and working closely with multidisciplinary design teams.

Key Responsibilities

• Execute verification planning activities for analog/mixed-signal (AMS) environments related to high-speed Ser Des and complex IP.
• Identify, debug, and communicate design bugs in collaboration with analog, digital, and mixed-signal designers.
• Contribute to methodology development, partnering with internal teams and EDA vendors to enhance AMS verification flows.
• Document and maintain progress across verification tasks, methodology efforts, and bug tracking.

Skills & Technical Expertise

• Solid scripting skills (Python, Tcl, Perl, etc.) for simulation automation and regression workflows.
• Understanding of fabrication processes, process corners, performance variation, and simulation setup.
• Strong knowledge of electrical and discrete testbench concepts, run-time optimization, and solver configuration.
• Proficiency with modern simulation tools, mixed-signal debuggers, and analysis frameworks.
• Familiarity with revision control systems and collaborative development practices.
• Strong communication and reporting skills for cross-functional team interaction.

Experience

• Hands‑on experience with digital, analog, or mixed‑signal verification, including:
• Compile/elaboration debugging and mixed-signal integration workflows
• Experience with behavioral modeling and basic understanding of analog building blocks.
• Background using fast analog and digital solvers (e.g., AMS‑capable simulators) for mixed‑signal validation.
• Experience developing constrained‑random test benches and coverage‑driven methodologies.
• Familiarity with System Verilog Assertions, property checking, and assertion‑based verification.
• Experience with schematic‑driven and mixed‑signal design environments (Virtuoso‑style frameworks).
• Exposure to high-speed communication systems such as Ser Des is an advantage.
• Strong digital verification foundation with experience in Specman/e, UVM, or mixed‑signal methodologies.

• Mid-Senior level

• Full-time

• Engineering and Design
• Industries:
  Semiconductor Manufacturing, Computers and Electronics Manufacturing, and Computer Hardware Manufacturing

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