Principal ASIC DFT Design Engineer - Terawave

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-basedconnectivitywith

TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6

Tbpsanywhere on Earth.

This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations.

As a Principal ASIC DFT Designer on the ASIC Engineering SOC Team, you will own design for test architecture for the Tera Wave System on Chip (SOC) program. You will define the test strategy for large multi-block SOC designs, implement scan, compression, and built in self test infrastructure, and deliver the test vectors that qualify silicon on automated test equipment. This is a senior individual contributor role with technical leadership scope and no direct reports.

Your work spans specification through silicon bring up, including ATE pattern debug and support for defect and yield analysis, and it directly determines test quality and manufacturability for the program.

• Define DFT architecture and test strategy for large multi-block SOC designs
• Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms
• Implement scan chain insertion, test clock control, and on chip compression logic
• Design memory and logic built in self test infrastructure for embedded memories and logic
• Generate and validate DFT vectors for silicon bring up and production test programs
• Debug ATE pattern failures and drive resolution with design and product engineering teams
• Support defect analysis and yield improvement using test coverage and silicon failure data
• Review test coverage and DFT timing metrics with physical design and verification teams

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical field
• Minimum 10 years of experience in design for test for complex digital SOCs
• Experience defining DFT architecture and specifications for large multi-block SOC designs
• Experience with DC and AC scan design and memory built in self test implementation
• Experience generating ATPG patterns for automated test equipment and debugging ATE patterns

• Master’s degree in Electrical Engineering, Computer Engineering, or related technical field
• Experience with logic built in self test implementation and signature based test methodologies
• Experience with defect analysis and yield improvement for advanced process node silicon
• Experience with hierarchical DFT and IEEE 1500 or IEEE 1687 test access standards
• Experience with commercial DFT tool flows such as Tessent, DFTMAX, or Modus
• Experience with test time and test cost reduction through pattern and compression optimization
• Strong written and verbal communication skills for presenting test strategy to technical stakeholders

Base Pay Range for:

CA applicants is $ - $ WA applicants is $ - $

Other site ranges may differ

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway.

You may be just the right candidate for this or other roles.