Senior PCIe Subsystem RTL Lead AI​/HP SoCs

TYLsemi is seeking a Principal PCIe Sub-system Front-end RTL lead to drive the PCIe microarchitecture for next-gen chiplet-based SoCs. You will own from PHY to Transaction Layer, coordinating wrapper RTL, telemetry, and integration with the chiplet fabric.

You will mentor RTL engineers, collaborate on UVM verification, and work with the engineering team to meet timing and power-management goals for high-performance compute and AI silicon.

We invite applications for the Senior PCIe Subsystem RTL Lead for AI/HP SoCs position located in United States.

This is a strong opportunity to take on the Senior PCIe Subsystem RTL Lead for AI/HP SoCs role at TYLsemi.

As a Senior PCIe Subsystem RTL Lead for AI/HP SoCs, you will play an important part at TYLsemi in United States.

The following role is for a Senior PCIe Subsystem RTL Lead for AI/HP SoCs with TYLsemi.