Design Engineer, IC Layout

Position: Staff Design Engineer, IC Layout

Impinj delivers the Physical Intelligence that connects the physical world to the AI-powered digital world, fueling automated workflows and improving consumer experiences. From retail merchandise and groceries to packages and shipping pallets, Impinj products and solutions identify and track tens of billions of everyday items, providing real-time operational insights about every item enterprises make, move and sell. We are, quite literally, the eyes and ears of smart enterprise systems.

Come help us build technology and solutions that enable businesses to visualize everything, waste nothing and act instantly.

Team Overview:

The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team, internationally. The team is responsible for delivering tape-outs for RFID products, test chips, reader ICs, and DOEs (design of experiments) work that sits at the center of how Impinj brings new silicon to market.

Layout decisions made by this team directly influence the power efficiency, cost, and time-to-market of every piece of silicon we ship, making the group's work foundational to Impinj's mission. The team operates with a continuous-improvement mindset, adapting quickly and challenging each other to remain best-in-class in both quality and speed, with meticulous attention to detail to ensure designs have long-term reliability and zero defects, at production volumes in the many billions and eventually trillions of tags per year.

What You Will Do:

• Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for both high-performance RF as well as ultra-low power and compact RFID
• Work closely with the analog and digital design teams on floor planning, pin placement, power supply strategy and signal distribution between blocks
• Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling
• Participate in schedule meetings coordinating layout and floorplan activities

What You Will Bring:

• Bachelor’s degree in computer or electrical engineering and 8+ years of experience
• Experience in custom analog, RF, and mixed-signal layout
• Ability to collaborate with other layout engineers on the top-level IC floorplan, partnering with circuit designers to resolve complex problems
• Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm for ultra-low-power and high-fidelity applications
• Knowledge of analog layout challenges and layout-dependent effects in advanced processes — noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring — along with proficiency in mitigation techniques such as guard rings, DNW, PN junctions, parasitic management, signal integrity, reliability (EMIR), and ESD
• Proficiency with the use of Cadence Virtuoso layout editor and Cadence/Siemens layout verification tools (including PVS and Siemens Calibre DRC/LVS). Ability to interpret and correct ERC, DRC and LVS error reports
• Excellent communication and collaboration skills
• Strong technical project management skills

The benefits listed below may vary depending on the nature of your employment with Impinj and the country where you work.

The typical base pay range for this role across the US is $136,000 - $204,000
. Individual base pay depends on various factors such as complexity and responsibility of role, job duties, requirements, and relevant experience and skills. Both market wage data and the mid-point of the pay range is reviewed and used as the starting point for all new hire offers. Offers are made within the base pay range applicable at the time. At Impinj certain roles are eligible for additional…