DFT Design Engineer

Overview

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design‑for‑Test (DFT) and Design‑for‑Debug (DFD) features for complex state‑of‑the‑art APU computing, game console and GPU graphics products.

It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.

DFx (DFT, DFD) is a niche field of ASIC design where essential functionality is added to support semiconductor productization including manufacturing test, yield improvement and board debug. A DFT designer would need to factor many multi‑dimensional issues such as power, area and timing. Our work is a key contributor to delivering a high‑quality design and can improve AMD’s operating expenses in the millions.

• Understand Design‑for‑Test (DFT) and Design‑for‑Debug (DFD) architecture
• Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem
• Perform scan ATPG design rule checking, pattern generation, simulation and coverage analysis
• Collaborate with IP teams to configure and embed DFT RTL
• Setup and execute design checks using both industry standard and in‑house tools.
• Deliver Perl, TCL scripts that provide scalable solutions key to DFT implementation
• Create block‑/chip‑level Design Verification (DV) test plan
• Develop test cases, behavioral functional models and testbench
• Verify block‑/chip‑level DFT/DFD features
• Monitor CAD and/or IP regression results, debug failures and analyze coverage

• Experience with Perl/Shell scripting and C
• Digital circuits and VLSI knowledge
• Experience with Verilog environment is an asset
• Strong problem‑solving skills
• Good object‑oriented programming skills (C++) is a must
• Good written and oral communication skills
• Team player with strong interpersonal skills
• Industry DFT experience

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

• Seniority level:
  Mid‑Senior level
• Employment type:
  
  Full‑time
• Job function:
  Semiconductor Manufacturing

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