Memory PHY RTL Design Lead

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THE ROLE:

The Memory PHY team is looking for a highly skilled Senior / Lead Design Engineer for RTL development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:
You are an experienced digital design engineer with deep knowledge of DDR PHY/controller architecture and JEDEC specifications. You are comfortable taking technical ownership, making architectural decisions, and mentoring others. You are a self-starter who can introduce and deploy new EDA tools and flows into the design environment. You communicate clearly, collaborate effectively across disciplines, and enjoy solving complex technical and methodological problems.

KEY RESPONSIBILITIES:

Own microarchitectural design and RTL implementation of major IP features and sub-systems. Synthesis, STA, CDC/RDC, UPF Design/Simulation, Power optimization, Gate sim. Drive PHY digital architecture development from pathfinding and high-level architecture to RTL coding, verification, and support for physical implementation. Interpret and apply JEDEC DDR/LPDDR specifications to ensure standards-compliant PHY and controller behavior. Collaborate closely with the Firmware team to define, implement, and optimize firmware sequences and algorithms.

Analyze RTL design for power, performance, and area (PPA); guide optimization strategies and tradeoffs. Partner with Design Verification teams to define verification strategies and ensure robust coverage of design features (including UVM-based environments). Drive timing synthesis, constraints definition, and support backend teams through physical implementation and signoff. Lead and participate in design specification reviews, microarchitecture reviews, and RTL code reviews;

enforce high-quality design practices. Introduce, evaluate, and deploy new EDA tools, scripts, and methodologies into the workflow to improve productivity and quality. Provide technical leadership, mentorship, and day-to-day guidance to junior and intermediate engineers. Collaborate with cross-functional teams (architecture, analog/mixed-signal, PD, FW, verification) to resolve complex integration issues.

PREFERRED EXPERIENCE:

Solid industry experience in digital design engineering, with a focus on complex SoC/IP blocks. Strong experience with DDR / LPDDR PHY and/or Memory Controller design, including:
Good working knowledge of JEDEC DDR/LPDDR specifications. Experience translating spec requirements into microarchitecture and RTL. Excellent knowledge of Verilog and System Verilog for design; C/C++ experience is a strong plus. Proficient with scripting for automation and flow development; experience with Python is preferred. Demonstrated ability to bring up and deploy new EDA tools and methodologies into an existing design flow (e.g., lint/CDC/Formal, power analysis, synthesis, static timing, coverage, regression infrastructure).

Proficient in debugging firmware and RTL code using simulation and waveform tools. Experience working with UVM testbenches and verification environments. Comfortable working in Linux-based development environments;…