Physical Design Engineer - Chip Floorplanning

Position: Physical Design Engineer - Full Chip Floor planning
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE
We are seeking an adaptive, self-motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive AMD’s capabilities in delivering high-performance, power-efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success. In this role, you will be responsible for full-chip floor planning, physical implementation, timing closure, and power optimization across complex SoC designs.

THE PERSON
You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have experience in full-chip floor planning, synthesis, place and route, timing closure, and power optimization. You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem-solving abilities, are eager to learn, and thrive in tackling complex design challenges.

KEY RESPONSIBILITIES

Define chip-level partitioning, block placement strategy, and macro integration to meet design and performance goals

Demonstrate hands‑on expertise in full-chip floor planning, including feed through topology planning, repeater insertion, top‑level port/pin assignment and alignment, and source‑synchronous bus layout

Optimize full-chip floorplan for timing, power, and area across the entire chip

Collaborate closely with RTL, physical design, and architecture teams to gather and implement design requirements effectively

Conduct layout feasibility studies through what‑if analysis and trade‑off evaluations

Utilize industry‑standard EDA tools such as Cadence Innovus, Synopsys ICC, and Calibre for physical implementation and verification

Develop and maintain automation scripts using Tcl, Perl, and Python to enhance floor planning efficiency and consistency

Apply low‑power design techniques; familiarity with voltage domain crossing checks is a strong asset

PREFERRED EXPERIENCE

Extensive experience in SoC implementation and tapeout

Strong expertise in physical design methodologies and flows

Proficient with Synopsys Fusion Compiler (FC)

Solid understanding of SoC architecture and design, including AXI buses, source synchronous design, and test design

Highly committed to meeting project milestones with high‑quality timing constraint delivery

Experienced in complex SoC full‑chip timing floor planning and timing quality checks

Excellent communication skills; capable of working independently and collaboratively within a team

Proven ability to collaborate effectively with IP and PD teams for timing closure

Demonstrated leadership and strong teamwork capabilities

Skilled in script development using Perl and Shell; experienced in Verilog RTL design

ACADEMIC CREDENTIALS

Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering

LOCATION
Markham, ON

Benefits offered are described: AMD benefits at a glance.

EEO STATEMENT
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

#J-18808-Ljbffr