Memory Subsystem Design Verification Engineer

Memory Subsystem Design Verification Engineer

Overview

The Memory Subsystem team is hiring Verification Engineers to contribute to the definition, design, and development of high-speed LPDDR/DDR memory subsystem solutions and associated IP. This role includes verification across multiple product lines and pre-silicon production-level firmware co-verification using hybrid co-simulation environments and UVM.

• Design and implement advanced verification environments for memory subsystems and associated IP using System Verilog and UVM methodologies.
• Develop and maintain test benches, co-verification frameworks, and test suites aligned with evolving firmware features, ensuring comprehensive coverage and robust verification from IP and subsystem levels through production.
• Integrate and debug Memory VIP, analyze coverage metrics, manage regressions, and collaborate with cross-functional teams to deliver end-to-end verification solutions.
• Adapt to new tools and frameworks, contribute improvements, and document results to support efficient and scalable verification processes.

• Proficiency in C/C++, System Verilog, UVM (object-oriented design), and scripting languages (e.g., Python, shell).
• Experience in IP and subsystem verification with System Verilog/UVM and VCS.
• Background in testbench architecture, microarchitecture, and co-verification with firmware.
• Knowledge of code and functional coverage and how test plans map to cover goals.
• Ability to design and debug co-verification environments for production-level firmware.
• Experience developing transactor-based stimulus and maintaining test suites as features evolve.

• Experience building monitors/checkers and developing SVA/OVL and synthesizable assertions.
• Verification experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controllers.
• Experience verifying subsystems/components and applying methodologies to achieve subsystem verification.
• Familiarity with architectural models and System
  
  C.
• Experience with Zebu emulation for verification and debug.
• Firmware/hardware co-verification using UVM System Verilog, C-DPI, and gasket-structured test benches.
• Memory VIP integration, bring-up, and debug.
• End-to-end verification experience from front-end through lab bring-up.
• Understanding of synchronization techniques (e.g., handshakes, message passing) and hardware-level clocking, including multi-domain simulation synchronization.
• Experience with Git and Perforce.
• Managing regressions and coverage databases.
• SoC IP knowledge and a high-level understanding of the role and interfaces of each IP.

• Bachelors or Master's in electrical engineering, computer engineering, computer science, or a related field or equivalent practical experience in verification engineering.

Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Base pay range: $/yr - $/yr