More jobs:
Senior Design Verification Engineer — RTL/UVM SoC
Job Description & How to Apply Below
A global technology corporation seeks a Design Verification Engineer in Milan, Italy. Ideal candidates will define verification methodologies and implement test plans for hardware designs, utilizing their expertise in System Verilog and UVM. Responsibilities include creating verification environments and collaborating with cross-functional teams. Applicants should have a Bachelor's degree in Electrical Engineering or a related field, with a minimum of 7 years of experience in semiconductor design verification.
Strong communication and debugging skills are essential for this role.
#J-18808-Ljbffr
Position Requirements
10+ Years
work experience
Note that applications are not being accepted from your jurisdiction for this job currently via this jobsite. Candidate preferences are the decision of the Employer or Recruiting Agent, and are controlled by them alone.
To Search, View & Apply for jobs on this site that accept applications from your location or country, tap here to make a Search:
To Search, View & Apply for jobs on this site that accept applications from your location or country, tap here to make a Search:
Search for further Jobs Here:
×