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Job Description & How to Apply Below
Join to apply for the ASIC Digital Design, Sr Staff Engineer - 13027 role at Synopsys Inc
About the Company
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
About You
You are a passionate, highly skilled digital design and verification engineer with over a decade of hands‑on experience in ASIC development, system validation, and emulation. You thrive in collaborative, fast‑paced environments and are energized by solving complex technical challenges. Your background demonstrates deep expertise in hardware emulation platforms (such as Zebu and HAPS), system‑level prototyping for protocols like PCIE, Ethernet, and USB, and a solid grasp of digital signal processing concepts.
You have a proven track record of architecting, modeling, and verifying high‑speed data recovery circuits, and you bring advanced scripting abilities in Shell, Perl, Python, and C++ to automate and optimize workflows.
You are adept at building robust verification environments using UVM methodology and System Verilog, integrating VIPs, and developing comprehensive test plans. You understand the importance of clear communication and effective organization, effortlessly bridging the gap between cross‑functional teams and customers. Your proactive nature, self‑motivation, and commitment to design quality empower you to deliver innovative solutions under tight deadlines. You value opportunities to learn from industry veterans, continuously expand your expertise, and contribute to next‑generation silicon architectures that drive technology forward.
You are dedicated to fostering an inclusive workplace and embrace diversity in thought and background. You seek a role where your work makes a tangible impact on flagship products and customer success, and you are eager to be a part of a team that values collaboration, growth, and continuous learning.
What You’ll Be Doing
Designing and implementing digital architectures for high‑end mixed‑signal SoCs, including HPC PAM4 DSP‑based Ser Des PHY products.
Developing and executing hardware emulation strategies using FPGA platforms such as Zebu and HAPS.
Building and validating system‑level prototypes for industry‑standard protocols (PCIE, Ethernet, USB, etc.).
Creating and maintaining robust verification environments with UVM methodology, including testbench development and VIP integration in System Verilog.
Authoring and optimizing scripts in Shell, Perl, Python, and C++ to automate design, verification, and testing workflows.
Collaborating closely with cross‑functional teams to ensure design quality, resolve technical challenges, and meet project milestones.
Performing functional and performance tests on test‑chips, analyzing results, and driving improvements to architecture and implementation.
The Impact You Will Have
Shape the architecture and quality of Synopsys’ next‑generation flagship silicon IP products.
Accelerate time‑to‑market for high‑performance SoCs by enabling robust emulation and validation methodologies.
Enhance product reliability and customer satisfaction through comprehensive testing and verification.
Drive innovation in digital signal processing and data recovery circuits, influencing industry standards.
Facilitate cross‑team collaboration, knowledge sharing, and continuous improvement in design practices.
Support customer engagement by delivering differentiated solutions and technical expertise.
Contribute to the diversity and inclusivity of the engineering team, fostering a culture of respect and opportunity.
What You’ll Need
10+ years of experience in ASIC design, verification, or system validation roles.
Expertise with hardware emulation platforms (Zebu, HAPS) and FPGA‑based prototyping.
In‑depth knowledge of system‑level validation for PCIE, Ethernet, USB, and related protocols.
Proficiency with…
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