Senior Principal Verification Engineer

Sr Principal Digital Verification Engineer

Location:

Montreal, Ottawa, Toronto

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview
This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The candidate will primarily be responsible for leading a team of engineers in the verification of digital RTL and development of re‑usable verification components and environments.

The successful candidate will be a highly motivated self‑starter with strong leadership qualities. It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

The ideal candidate will have a fundamental understanding of the end‑to‑end verification flow so they can accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status. The most successful candidates will demonstrate excellent command of fundamental logic principles as well as excellent problem‑solving and communication skills.

The candidate should be able to work as part of a focused team of engineers and collaborate successfully with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.

The Cadence Silicon Solutions Group (SSG) develops leading‑edge Intellectual Property (IP) for a variety of high‑tech markets.

Job Responsibilities

Project planning and progress tracking

Leading a team of 5–15 engineers in the execution of verification tasks

Definition and management of verification plans (vPlans) using Cadence vManager tools

Architecture of verification environments for complex IP such as multi‑protocols PHY

Development of UVM‑SV scoreboards for self‑checking regressions

Development of functional coverage as part of metric‑driven verification environments

Development of System Verilog assertions for use in formal and simulation environments

Creation and management of automated regression environments, e.g., Jenkins

Participation in technical review meetings and checklist reviews

Close collaboration with design engineers to debug complex test scenarios

Job Qualifications

Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline

12+ years’ experience in the microelectronics/EDA industry

Experience with Verilog RTL design (essential)

Experience with metric‑driven verification (MDV) (essential)

Excellent oral and written English (essential)

Exposure to standard protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI

Self‑motivated with excellent planning, interpersonal, and communication skills

Cadence is an equal‑opportunity employer committed to hiring a diverse workforce.

Titre:
Concepteur Principal Senior en vérification numérique
Localisation:  Montreal, Ottawa, Toronto

Description
Cadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie.

Le candidat aura la charge de diriger une équipe dans la vérification de modules numériques RTL et du développement de modules de vérification réutilisables.

Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élab oration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture.

Le candidat devra posséder des connaissances avancées des méthodes de design et de vérification des composantes numériques. Il devra être autonome, dynamique et démontrer de très bonnes qualités de communication.

Le groupe de design IP est une équipe multidisciplinaire composée d’ingénieurs provenant de divers sites à travers le monde. Faisant partie du groupe de vérification, le candidat sera amené à col laborer avec diverses disciplines et phases de la réalisation complète d’IP matériel : design numérique et analogique, design…