Senior Physical Design Engineer – SoC Tapeout Expert
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Engineering
Hardware Engineer, Electronics Engineer
Job Description & How to Apply Below
Rivian is seeking a seasoned Physical Design Engineer to drive all phases of physical design for high‑performance SoCs, from RTL to GDSII, in the San Francisco Bay Area. You will collaborate with Foundry, architecture, and packaging teams to deliver tapeout‑ready silicon.
Ideal candidates have 12+ years in chip design, strong CPU/SoC expertise, and a track record of successful tapeouts. The role requires hands‑on PPA optimization, EM‑IR sign‑off leadership, and cross‑functional teamwork.
We are seeking a motivated Senior Physical Design Engineer – SoC Tapeout Expert to join Rivian-3 in Palo Alto, CA, United States.
We aim to respond to suitable candidates as soon as possible.
Full responsibilities and requirements are described in the listing above.
Learn more about the Senior Physical Design Engineer – SoC Tapeout Expert role in the description above.
Position Requirements
10+ Years work experience(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).