Physical Design Engineer

Job Title:
Physical Design Engineer

Location:
San Diego, CA, Santa Clara, CA, Austin, TX, Chandler, AZ (100% Onsite)

Duration : 12 Months

Role Overview

As a Physical Design Engineer you are responsible for transforming high-performance, low-power digital designs from synthesized netlists into manufacturing-ready silicon (Netlist-to-GDSII). You will work on cutting-edge mobile, automotive, compute (Snapdragon/Oryon CPU, Adreno GPU, NPU, and modem), and AI SoCs on advanced foundry nodes (e.g., 5nm, 3nm, and below).

Key Responsibilities

• Execute complete physical design flows including partition-level and full-chip floor planning, power grid synthesis, placement, Clock Tree Synthesis (CTS), routing, and post-route optimization.
• Timing & Signal Integrity Closure:
  Perform multi-corner, multi-mode (MCMM) Static Timing Analysis (STA), constraint validation, setup/hold closure, signal integrity (SI) glitch/crosstalk mitigation, and clock-skew optimization.
• Power & IR-Drop Optimization:
  Implement low-power methodologies (UPF/CPF, power gating, multi-Vt, voltage domains) and drive static/dynamic IR-drop and electromigration (EM) analysis and remediation.
• Physical Verification & Sign-off:
  Run and debug Design Rule Checks (DRC), Layout Versus Schematic (LVS), Antenna, Electrical Rule Checks (ERC), and dummy metal fill to meet stringent external foundry requirements.
• Cross-Functional Collaboration:
  
  Partner with RTL design, DFT (Design-for-Test), CAD, architecture, and foundry integration teams to deliver optimal Power, Performance, and Area (PPA) trade-offs.
• Flow & Automation Development:
  Develop and maintain automation scripts to enhance turn-around time (TAT), improve methodology robustness, and resolve routing/timing bottlenecks.

Required Qualifications & Skills

EDA Tool Proficiency:

• Place & Route:
  Synopsys ICC2 / Fusion Compiler or Cadence Innovus.
• Timing Sign-off:
  Synopsys Prime Time / Prime Time-SI or Cadence Tempus.
• Power/Reliability:
  Ansys Red Hawk / Red Hawk-SC or Cadence Voltus.
• Physical Verification:
  Siemens Calibre (nmDRC, nmLVS, PERC) or Synopsys IC Validator.
• Semiconductor Fundamentals:
  Solid grasp of CMOS digital logic, FinFET/GAAFET technology characteristics, standard cell libraries, and RC parasitics.
• Low-Power Design:
  Practical experience with UPF/CPF, multi-voltage domains, retention cells, and power switch fabrics.
• Scripting & Automation:
  Strong scripting skills in Tcl, Python, Perl, and Unix/Linux shell for flow customization and data mining.

Education & Experience

• Education:
  
  Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, VLSI Design, Computer Engineering, or a related field.

Experience Levels:

• Engineer: 0–3 years of experience in ASIC physical design/STA.
• Senior Engineer: 3–7 years with proven block-level ownership and tape-out experience on FinFET nodes.
• Staff / Principal / Lead Engineer: 8+ years leading full-chip assembly, hierarchy planning, complex SoC integration, and sign-off closure.

Preferred Qualifications

• Hands-on tape-out track record on sub-7nm (5nm/4nm/3nm) advanced process nodes.
• Experience with high-frequency CPU cores, GPU blocks, or high-speed interface subsystems (PCIe, LPDDR, USB).
• Familiarity with Machine Learning/AI-driven PnR tool flows and automated PPA closure techniques