Principal Engineer, Physical Design; ASIC Place & Route

Position: Principal Engineer, Physical Design (ASIC Place & Route )
Overview

of Role As a Principal Physical Design Engineer, you will serve as a foundational pillar in translating complex architectural concepts into high-yield, production-ready silicon. Operating at the cutting edge of semiconductor design, you will spearhead end-to-end netlist-to-GDSII implementation for ultra-large-scale, high-performance computing (HPC) and AI silicon architectures. In this role, you will define the boundaries of achievable PPA (Power, Performance, and Area) across the industry’s most advanced process nodes.

Based out of our San Jose Center of Excellence and working closely with our customer partners, you will collaborate with cross-functional architecture, CAD, and DFT teams to push physical design methodologies forward. You will lead technical execution on critical block- and chip-level domains, tackling non-trivial physical and electrical challenges inherent to deep-submicron physics. We are seeking a seasoned, intellectually curious individual who thrives on engineering rigor and structural precision.

This position follows a high-impact, hybrid collaboration model (4 days on-site) designed to accelerate tight engineering feedback loops and direct technical partnership.

Responsibilities

Drive full-flow RTL/Netlist-to-GDSII physical implementation, taking high-complexity, multi-million gate blocks through synthesis, floor planning, placement, clock tree synthesis (CTS), routing, and final signoff. Architect highly optimized floor plans from scratch, establishing robust power delivery networks (PDN) while strategically minimizing congestion, channel utilization, and macro placement overhead. Synthesize customized, low-skew, and variation-aware clock tree architectures designed to maximize frequency margins under aggressive power budgets.

Execute advanced timing closure and post-route optimization workflows, methodically engineering functional and timing engineering change orders (ECOs) across multi-corner, multi-mode (MCMM) scenarios. Mitigate complex electrical and physical phenomena by leading deep-dive signal electromigration (EM), dynamic cross-talk noise, and power rail integrity (IR drop) analyses to guarantee target reliability margins. Direct physical verification signoff by debugging and rectifying complex DRC, LVS, ERC, and antenna violations in close alignment with advanced foundry design rule manuals (DRMs).

Develop and deploy bespoke automation frameworks and design methodology enhancements using Tcl and Python/Perl to streamline tapeout velocity and improve cross-project PPA predictability.

Minimum Qualifications

Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Microelectronics, or a closely related technical field. 10+ years of direct, hands-on experience in full-chip or block-level physical design implementation and signoff with a proven track record of successful tapeouts. Demonstrated mastery of industry-standard EDA tool suites (e.g., Synopsys Fusion Compiler/ICC2, Prime Time, StarRC; Cadence Innovus, Tempus, Voltus; Siemens Calibre). Proven track record implementing designs in TSMC N16/N12 or below, with deep knowledge of advanced FinFET parasitic extraction, multi-patterning, and variability effects.

Proficient scripting ability in Tcl, Perl, and/or Python to construct, maintain, and debug complex automation pipelines and signoff scripts. Strong communication and cross-functional leadership skills, with the flexibility to work regularly on-site and at key customer partner facilities across the South Bay Area.

Preferred Qualifications

Hands-on physical design and tapeout experience on advanced FinFET/GAA nodes (TSMC N5, N4, N3, or below). Advanced expertise in low-power methodology implementation, including multi-voltage…