Technical Manager, Physical Design Verification Lead

Overview of Role
TSMC Technology Inc. is at the forefront of semiconductor innovation, delivering cutting-edge solutions that power the next generation of technology. We are seeking a highly experienced and motivated Physical Design Verification Lead to join our dynamic team, working closely with a key customer on advanced designs in N2P/A14 technology nodes. This is an exceptional opportunity to drive critical verification efforts on state-of-the-art technology nodes and contribute to successful production tapeouts.

Responsibilities
As a Physical Design Verification Lead, you will be a pivotal member of our team, responsible for ensuring the robust physical integrity and performance of high-performance chip designs. You will lead comprehensive physical verification efforts from block-level implementation through to final production tapeout, playing a crucial role in achieving silicon success. Your expertise will directly impact the quality and reliability of our advanced products.

• Lead and execute
  end-to-end physical design verification for CPU blocks, culminating in successful production chip tapeouts.
• Collaborate closely with the STA team
  to implement Engineering Change Orders (ECOs) for critical timing closure.
• Perform in-depth analysis and resolution
  of Signal EM/Noise and Power IR/EM issues.
• Manage comprehensive analysis and cleanup
  for all physical verification checks, including DRC, LVS, ERC, and Antenna violations.
• Achieve final physical verification sign-off
  across all design metrics.
• Oversee the implementation
  of customized Clock Tree Structures (CTS) and advanced Place & Route strategies.
• Optimize block-level floor plans
  , meticulously analyzing and ensuring high-quality design partitioning.
• Provide technical leadership and mentorship
  to junior engineers.

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 10-20 years of hands-on experience in physical implementation and verification roles.
• Demonstrated expertise
  with major Electronic Design Automation (EDA) tools (e.g., Innovus/ICC2, Calibre) and established design flows.
• Extensive experience
  in chip integration and sign-off procedures.
• Proven experience with advanced technology nodes, specifically TSMC N7 or below.
• Proficiency in scripting languages, particularly TCL, Perl, and Python, for automation and flow enhancement.
• Ability and willingness to work full-time
  at a customer site located in the South Bay area.

Preferred Qualifications

• Direct experience
  with TSMC N2 technology nodes.
• In-depth knowledge
  of CPU implementation methodologies.
• Expertise in advanced timing sign-off methodologies
  and techniques.
• A strong track record
  of successful production tapeouts for multi-million gate designs.
• Prior experience leading physical verification efforts or small teams.

Company Description

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that…