Physical Implementation Architect

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At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture.

We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

As a Physical Implementation Architect, you will lead all aspects of RTL development, physical implementation during IP development to closure at SoC level, from RTL optimization through all stages of Physical Design closure. You will set technical direction, mentor engineering teams, and ensure best-in-class power, performance, and area (PPA) for high-speed (>2GHz) designs with complex I/O clocking.

As a Physical Implementation Architect, you will collaborate with IP architects, RTL designers, physical design engineers, and NBIO IP team managers. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team.

• Lead RTL optimization for physical implementation working with RTL team, starting from Architecture to final Physical Design closure, finding appropriate tradeoff for Power, Performance, Area (PPA). Drive methodology and execution of the overall team’s execution through all stages of implementation synthesis, floor planning, placement, clock tree synthesis, routing, full-chip timing, closure for advanced SoC projects.
• Architect and implement reference methodologies and automation scripts for global SoC development.
• Provide technical leadership for multiple I/O protocols, chiplet interfaces, including PCIe, UCIe, UAlink, Ethernet, and Infinity Fabric link-layer.

• Mastery of RTL optimizations to facilitate PD closures.
• Deep understanding of CDC, RDC, LINT, STA constraints development.
• Logical equivalence checking using industry standard tools.
• Closure of last mile timing, including functional ECO, and timing closure.
• Automation using TCL and Python, including use of AI for Design.
• 15+ years of industry experience in physical implementation leadership.
• Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs.
• Deep expertise in physical design methodologies for high-speed (>2GHz) SoCs.

• MS, or PhD in Electrical or Computer Engineering.

Markham, Ontario;
Vancouver, Canada; U.S. locations

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.

We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.