Senior DFT Architect Multicore SoCs

My client is seeking a highly skilled and experienced Principal Design for Test (DFT) Engineer to join their innovative and dynamic team in Zurich. In this role, you will play a critical part in architecting and implementing advanced testability solutions for our cutting‑edge multicore in‑memory‑compute System‑on‑Chip (SoC) technology. This is an exceptional opportunity to contribute to groundbreaking advancements in the semiconductor industry while working in a collaborative and forward‑thinking environment.

Visa sponsorship will not be considered.

• Developing and implementing comprehensive DFT strategies for multicore in‑memory‑compute So Cs
• Collaborating with cross‑functional teams to ensure the seamless integration of test solutions into the design process
• Driving innovation by advancing testability methodologies and infrastructure to enhance product quality and reliability
• Conducting fault simulation, silicon debug, and gate‑level verification to ensure robust and efficient designs
• Utilising industry‑standard tools and techniques to optimise test coverage and performance

• Senior‑level expertise in DFT engineering with a proven track record of success in the semiconductor industry
• Proficiency in System Verilog RTL, TCL, Python, and Unix/Linux
• In‑depth knowledge of hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate‑level verification
• Familiarity with industry‑standard DFT tools such as Siemens, Cadence, or Synopsys

If you are ready to take on this exciting challenge and contribute to the future of semiconductor innovation, we encourage you to apply. Join us in shaping the next generation of AI technology!

For an initial conversation, please contact Ane@ IC Resources with your CV and a time for a 15 min call!

• Mid‑Senior level

• Full‑time

• Engineering and Information Technology

• Staffing and Recruiting