Analog Design Engineer Agoura Hills, CA)

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Date: Oct 12, 2026

Location: Agoura Hills, CA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

TERADYNE
, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respect their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE). The ideal candidate will have experience in CMOS circuit design and successful ASIC tape‑outs, along with strong analytical, problem‑solving, and communication skills. This role offers the opportunity to collaborate across multidisciplinary teams while leveraging AI‑powered tools, automation, and data‑driven methodologies to accelerate semiconductor innovation.

A passion for emerging technologies, continuous learning, and technical excellence is highly valued.

Responsibilities include:

• Design and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
• Validate and integrate designs using Cadence EDA tools across PVT corners, while supporting layout and ASIC integration.
• Participate in silicon characterization, debug, validation, and production test activities.
• Develop automation, scripting, and AI‑assisted workflows to improve design productivity, verification, and data analysis.
• Collaborate across design, validation, test, and EDA teams to advance AI‑enabled IC design methodologies.

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. Ifyou’reready to join usinthis mission, take a closer look at theminimumcriteria for the position.

• MSEE or higher preferred, with 2+ years of experience in mixed-signal IC design and characterization;
  FinFET (16nm and below) experience is a plus.
• Strong knowledge of high-frequency analog/mixed-signal IC design, including PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, and CML designs.
• Solid understanding of CMOS device physics, semiconductor processes, PDKs, thermal effects, and electromagnetic principles.
• Experience throughout the IC development lifecycle, including silicon characterization and laboratory measurements.
• Familiarity with AI/ML techniques, generative AI, and large-scale data analysis for semiconductor design, validation, and test applications.
• Proficiency in scripting languages (Python/SKILL/Ocean) for automation and data analysis;
  Verilog/Verilog-A experience is a plus.

We are an equal-opportunity employer and value diversity at our…