GPIO​/Interface I​/O Design Engineer

Team:
Enablement / Foundation & Interface IP Development

Location:

Albany (NY), Santa Clara (CA), Tokyo (Japan), or Chitose (Japan)-

Rapidus Corporation is developing next-generation semiconductor technologies at the 2 nm node and beyond
. We are seeking talented GPIO / Interface I/O Design Engineers to join our Enablement organization and develop advanced I/O solutions for leading-edge foundry technologies.

The role covers the design and development of GPIO, general-purpose I/O, and interface I/O circuits
, including input/output buffers, level shifters, high-speed I/O building blocks, and associated ESD and reliability structures.

Candidates with expertise in I/O circuit design, custom circuit design, layout, signal integrity, reliability, or DTCO are encouraged to apply. You will work closely with process, device, reliability, package, PDK, EDA, and IP teams to develop robust and scalable I/O solutions for 2 nm and future technology generations.

• Design and optimize GPIO and interface I/O circuits for 2 nm and beyond technology nodes.
• Develop I/O building blocks including input/output buffers, drivers, receivers, level shifters, pre-drivers, termination circuits, and other interface-related circuits
  .
• Perform transistor-level circuit design and HSPICE simulations across PVT conditions to evaluate performance, power, leakage, signal integrity, and robustness.
• Develop and optimize I/O circuits supporting different voltage domains, drive strengths, signaling requirements, and interface applications
  .
• Collaborate with layout engineers on physical implementation, including pad structures, power distribution, guard rings, shielding, and ESD-sensitive layout
  .
• Work closely with process integration, device, and DTCO teams to optimize device options, I/O architecture, layout structures, and design rules for advanced technology nodes.
• Collaborate with reliability teams on ESD, latch-up, EM/IR, aging, and other reliability requirements for I/O circuits.
• Support signal integrity and power integrity (SI/PI) analysis and package/interface co-optimization as required.
• Support characterization and modeling of I/O cells for integration into customer design flows and IP libraries.
• Perform and support DRC, LVS, ERC, parasitic extraction, and reliability verification
  .
• Work with PDK and EDA teams to develop, validate, and improve I/O design, verification, characterization, and sign-off flows
  .
• Participate in test-chip planning, silicon characterization, qualification, failure analysis, and design-to-silicon correlation
  .
• Collaborate with external IP partners and customers to understand interface requirements and support integration of I/O solutions into advanced SoC designs.
• Contribute to the technology and IP roadmap for GPIO and interface I/O, including requirements for future technology nodes.

• B.S. or M.S. in Electrical Engineering, Electronics, or Microelectronics.
• 3+ years of experience in GPIO, I/O, interface circuit, analog/mixed-signal, or custom circuit design
  .
• Strong understanding of CMOS circuit design, device behavior, PVT variation, and circuit reliability.
• Experience designing one or more I/O circuit types such as drivers, receivers, level shifters, termination circuits, or voltage-domain interfaces
  .
• Hands-on experience with EDA tools for schematic design, simulation, layout, and verification, such as Cadence Virtuoso, HSPICE, and Siemens Calibre
  .
• Familiarity with DRC/LVS/ERC, parasitic extraction, EM/IR, and reliability verification
  .
• Ability to collaborate effectively across process, device, reliability, PDK, EDA, package, and IP development teams.
• Strong analytical, problem-solving, communication, and technical documentation skills in English.

• Experience with FinFET, nanosheet, or GAA technologies
  , particularly at advanced technology nodes.
• Experience with high-speed or advanced interface I/O in addition to conventional GPIO.
• Knowledge of ESD protection circuits, latch-up prevention, and I/O reliability design
  .
• Experience with multi-voltage I/O, level shifting, termination, impedance control, or signal integrity analysis
  .
• Familiarity with DTCO methodologies for I/O circuits, including device, circuit, layout, and process co-optimization.
• Experience with pad-ring, package, or chip-package co-design
  .
• Experience with I/O characterization, test-chip development, silicon validation, or qualification.
• Experience working with interface IP vendors or foundry…