ASIC Speed AMS Technical Leader
Job in
Allentown, Lehigh County, Pennsylvania, 18102, USA
Listed on 2026-10-08
Listing for:
CISCO Systems
Full Time
position Listed on 2026-10-08
Job specializations:
-
Engineering
Hardware Engineer, Electronics Engineer, Systems Engineer, Test Engineer
Job Description & How to Apply Below
The application window is expected to close on: 01/18/2027
Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.
Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.
Your Impact Build the optical backbone of the AI revolution. As our High-Speed Analog/Mixed-Signal Design Engineer, you will directly lead the electrical specifications, custom circuit design, and verification strategies for Cisco’s next-generation 800G, 1.6T, and beyond silicon photonics modules.
Operating within our best-in-class Silicon Photonics team, you will own the end-to-end development cycle for 100G/200G/400G per Lambda driver integrated circuits that seamlessly integrate with Cisco's core routing, switching, and datacenter platforms.
Your technical leadership will span critical execution phases from concept to production:
Datapath & Control Ownership:
Author high-performance mixed-signal datapath and low-speed control circuits for both receive and transmit paths—including photonic modulator drivers, serialize rs, PLLs, and TIAs—while rigorously optimizing for power, performance, testability, and cost.
Full-Chip Architecture & Integration:
Drive full-chip electrical specifications and comprehensive verification test plans, coordinating tightly across electrical, optical, and product architecture teams.
Bring-Up & Yield Enhancement:
Debug complex silicon and system-level bottlenecks hands-on during lab validation and bring-up phases to drive yield enhancements and failure analysis.
Technical Leadership & Mentoring:
Guide and mentor analog, digital, and validation engineers, elevating our team’s engineering excellence across next-gen data center architectures.
Minimum Qualifications Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of high-speed AMS design experience
Demonstrated expertise in high-speed optical transceiver design (modulator drivers, TIA, CDR, PLLs, ADC/DAC) and proficiency with industry standard tools (Cadence Virtuoso, Spectre, Caliber, System Verilog, Verilog-AMS)
Demonstrated ability to lead design teams through full tapeout cycle, making critical decisions with limited data and delivering successful silicon products
Proficiency in Python or C for design automation, scripting, and analytical tools
Preferred Qualifications
10-15 years of analog/mixed signal circuit design experience
Experience with silicon photonics driver ICs and direct-detect optical module architectures
Strong understanding of silicon photonics, optical subsystems, MSA standards (QSFP/QSFP-DD), and IEEE 802.3 specifications
Expertise in multiple high-speed PHYs, protocols and subsystems (Ser Des 112
Gbps/224
Gbps PAM4, Ethernet, UCIE, clock and data recovery systems, PLLs, ADC/DAC circuits)
Demonstrated experience in design for testability (DFT) and test methodology development for large mixed-signal designs
Proven experience with lab instrumentation (digital communication analyzers, real-time scopes, BERTs), SI/PI and test fixture/PCBFamiliarity with optical sub-component models (photodiodes, modulators) and Verilog-A modeling for AMS simulations
Strong collaborator and teammate with the ability to work across teams in multiple sites
Why Cisco? At Cisco, we’re revolutionizing…
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