ASIC Analog Senior Layout Engineer

The application window is expected to close on: 01/18/2027

Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact As a Senior Layout Engineer on the Silicon One Optics team, you won’t just be drawing polygons—you’ll be architecting the physical blueprint for the world’s fastest optical interconnects. You will own block-to-top integration for next-gen 100G, 200G, and 400G per lambda architectures, pushing silicon past standard limits. From initial floor planning to sign-off tapeout and silicon bring-up, your physical design decisions will directly power the future of global AI and data center infrastructure.

Power Next-Gen Optics:
Directly build and optimize complex analog and mixed-signal layouts for groundbreaking 100G–400G/lambda optical solutions.

Own the Silicon Lifecycle:
Drive full-flow execution from concept and floor planning through post-layout extraction, sign-off, tapeout, and post-silicon bring-up.

Solve High-Speed Challenges:
Master complex parasitic, signal integrity, and thermal tradeoffs alongside world-class circuit design, packaging, and CAD teams.

Set the Standard:
Shape design methodologies, mentor rising engineering talent, and raise the bar for physical execution across the group.

Minimum Qualifications Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience

Prior experience supporting block-level layout efforts through tapeout

Prior experience in physical verification and custom layout design, specifically with custom analog layout experience in FINFET 7nm, 5nm, or 3nmPrior experience with Cadence Virtuoso or similar custom layout tools

Preferred Qualifications Analog & Custom Layout Design:
Prior experience in device-level layout techniques (matching, symmetry, shielding, common-centroid, interdigitation, guard rings, isolation structures) and critical design concepts including parasitic control, thermal management, and signal integrity. Custom analog experience in TSMC 2nm or below is a plus.

EDA Tools & Signoff Flows:
Prior experience with EDA tools like Cadence Virtuoso and Calibre (or equivalent) in a Linux environment, with a strong command of physical signoff flows including DRC, LVS, ERC, parasitic extraction, and EM/IR analysis.

Tapeout & Automation:
Prior experience with ASIC/SoC tapeout processes and scripting capabilities (Python, Perl, or TCL) for layout automation.

Collaboration:

Prior experience working with cross-functional teams across multi-location teams.

Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team,…