PE Security Engineering

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Security Engineer to join our Security IP team in the Netherlands. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer.
As a Principal Security Engineer, the candidate will be reporting to the Manager, Security Engineering and is a full-time position. This engineer will work closely with other ASIC engineers and architects, as well as security, cryptography, verification and software engineers to architect, design, implement, and integrate digital hardware for the Crypto Manager Root-of-Trust product, and the DPA-resistant Cores line of products, including Post-Quantum cores.
Responsibilities   Research and develop secure cryptographic hardware IP blocks as part of Rambus Security’s IP portfolio
Develop side channel analysis (SCA) and fault injection attack (FIA) countermeasures for public- and symmetric-key cryptography hardware cores, verify against state-of-the-art SCA attack methodologies/techniques
Assist DPA and Fault evaluation
Invent, patent and publish new techniques in the field of SCA countermeasures, fault resistance and efficient hardware designs
Represent Rambus Security at international workshops and conferences
Micro-architectural definition/specification of Security IPs
RTL-level design in Verilog
Formal verification of designs, and assisting verification engineers with testbench bring-up, test plan creation, and debugging
Assist with EDA tool-related tasks, such as synthesis, static-timing analysis, logical equivalency checking, linting, continuous integration, and help improve flows and scripts
Assist with integration of Rambus Security technology into customer and partner ASIC design projects, in such areas as clocking and reset logic, memory interfaces, test interfaces, and system buses. Document and support Rambus designs for such integrations, including customer-facing meetings and presentations, and working with a technical writer in the production of technical documentation
Interface with internal and external back-end teams to provide guidance and support for back-end flows, especially place-and-route
Qualifications   Experience/Skills  MS/PhD degree in electrical or computer engineering required, PhD preferred
8 plus years working in secure hardware design, a PhD degree may substitute the work experience requirement
Design and implementation of efficient cryptographic algorithms that implement side channel analysis countermeasures
Knowledge of HW security architectures and IPs (secure MCU cores, cryptographic co-processors, secure memories, secure elements, smart cards)
Familiarity with front-end ASIC design flows, including design, simulation, assertions, formal verification, synthesis, timing analysis, logical equivalence checking, and linting/rule checking.

Experience with back-end flows, especially place-and-route, is beneficial.
Proven track record of on-time delivery of silicon-proven designs.

Demonstrated proficiency in Verilog and digital design.
Expertise in some or all of the following areas is beneficial:  Secure hardware design
Cryptographic algorithms and side-channel attacks
High performance CPU architecture and design.
IP core delivery and handoff issues.
Modern SoC design methodologies and architectures.
Low-power design techniques.
Clock and reset domain crossing techniques.
DFT, especially memory testing and characterization and/or Logic BIST methodologies.
Manufacturing test, device characterization and qualification, JTAG, reliability testing.

Hardware development experience in UNIX/Linux environments, including supporting tasks such as shell scripting and basic Perl scripts.
Ability to work with technical writers in the production of technical documentation.

Tools/Technologies  Verilog, System Verilog, Perl
Shell scripting, Python, Sage, Tcl
C, C++
MATLAB, Xilinx Vivado
OVL, SVA assertions
Unix, Linux
Unified Power Format (UPF)
Front-end ASIC design tools, especially  Synopsys Design Compiler
Cadence Genus
Synopsys Spyglass
Cadence Conformal(-LP)

ASIC simulation/verification tools, especially  Cadence…