Senior RTL Verification Engineer — FPGA​/ASIC

Fortaegis Technologies in Amsterdam is seeking a Design Verification Engineer to verify RTL designs for FPGA and ASIC products. The ideal candidate should possess over 5 years of experience in RTL verification and advanced knowledge of System Verilog and UVM.
This role involves developing verification strategies, maintaining verification environments, and collaborating with cross-functional teams. Join an innovative company at the forefront of semiconductor technology, where you can contribute to high-performance products and work in a dynamic team.

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