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System Verification Engineer; SystemVerilog & UVM

Job in 1013 ML, Amsterdam, North Holland, Netherlands
Listing for: Optimus Search
Contract position
Listed on 2026-07-13
Job specializations:
  • Engineering
    Test Engineer, Quality Engineering, Validation Engineer
Salary/Wage Range or Industry Benchmark: 70000 - 100000 EUR Yearly EUR 70000.00 100000.00 YEAR
Job Description & How to Apply Below
Position: System Verification Engineer (SystemVerilog & UVM) - 12 month contract
Job title - System Verification Engineer – Functional Safety (FuSa)
We are looking for an experienced System Verification Engineer – Functional Safety (FuSa) to join our SoC verification team. This role focuses on system-level verification of complex SoC subsystems and automotive use cases, with emphasis on functional safety verification, fault injection, and safety validation using simulation and hardware-assisted verification platforms.

The candidate will work closely with architecture, design, firmware, software, validation, and verification teams to ensure robust verification coverage and compliance with functional safety requirements.

Key Responsibilities

Develop and execute system-level verification plans for safety-critical SoC features.

Define and implement fault injection strategies and safety verification methodologies.

Verify safety mechanisms and safety-related system behavior.

Analyze architecture specifications and translate safety requirements into verification scenarios.

Debug complex failures involving hardware, firmware, software, and verification environments.

Manage and analyze regression results and drive closure of verification issues.

Collaborate across cross-functional teams to achieve verification signoff.

Required Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.

5+ years of experience in SoC/Sub-System/System Verification.

Strong understanding of Functional Safety (FuSa) concepts in automotive semiconductor development.

Experience with fault injection methodologies and safety verification techniques.

Strong expertise in System Verilog and UVM.

Experience with Cadence Xcelium and Cadence Verisium Manager.

Good understanding of compile-time and run-time switches.

Strong debugging skills in functional verification and fault simulations.

Scripting experience using TCL, Bash, Python, or Perl.

Understanding of AHB, AXI, and APB protocols.

Experience with regression management and root-cause analysis using Cadence vManager.

Preferred Qualifications

Exposure to ISO 26262 automotive safety standards.

Experience with complex SoC verification environments.

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